IDT82P2816BB IDT, Integrated Device Technology Inc, IDT82P2816BB Datasheet - Page 45

• Manufacturer Part Number: IDT82P2816BB
• Description: IC LIU T1/J1/E1 16+1CH 416-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82P2816BB

• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 1
• Voltage - Supply: 1.8V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: *
• Includes: Defect and Alarm Detection, Driver Over-Current Detection and Protection, LLOS Detection, PRBSARB / IB Detection and Generation
• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Power (watts): -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 82P2816BB

Inband Loopback (IB) Detection
length of the target activate/deactivate IB code can be 3 to 8 bits, as
determined by the IBAL[1:0]/IBDL[1:0] bits (b3~2/b1~0, IBL,...). The
content of the target activate/deactivate IB code is programmed in the
IBA[7:0]/IBD[7:0] bits (b7~0, IBDA/IBDD,...). Refer to Figure-25.
activate/deactivate IB code with no more than 10
certain period, the IB code is detected. The period depends on the
setting of the AUTOLP bit (b3, LOOP,...).
Loopback is disabled. In this case, when the activate IB code is detected
for more than 40 ms, the IBA_S bit (b1, STAT1,...) will be set to indicate
the activate IB code detection; when the deactivate IB code is detected
for more than 40 ms (T1/J1 mode) / 30 ms (E1 mode), the IBD_S bit (b0,
STAT1,...) will be set to indicate the deactivate IB code detection.
Loopback is enabled. In this case, when the activate IB code is detected
for more than 5.1 seconds, the IBA_S bit (b1, STAT1,...) will be set to
indicate the activate IB code detection. The detection of the activate IB
code in the receive path will activate Remote Loopback or the detection
of the activate IB code in the transmit path will activate Digital Loopback
(refer to Section 3.5.8.2 Remote Loopback & Section 3.5.8.3 Digital
Loopback). When the deactivate IB code is detected for more than 5.1
seconds, the IBD_S bit (b0, STAT1,...) will be set to indicate the deacti-
vate IB code detection. The detection of the deactivate IB code in the
receive path will deactivate Remote Loopback or the detection of the
deactivate IB code in the transmit path will deactivate Digital Loopback
(refer to Section 3.5.8.2 Remote Loopback & Section 3.5.8.3 Digital
Loopback).
or any transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the IBA_S/IBD_S bit
(b1/b0, STAT1,...) will set the IBA_IS/IBD_IS bit (b1/b0, INTS1,...) to ‘1’
Functional Description
IDT82P2816
The IB detection is in compliance with ANSI T1.403.
The extracted data is used to compare with the target IB code. The
During comparison, if the extracted data coincides with the target
If the AUTOLP bit (b3, LOOP,...) is ‘0’, Automatic Digital/Remote
If the AUTOLP bit (b3, LOOP,...) is ‘1’, Automatic Digital/Remote
A transition from ‘0’ to ‘1’ on the IBA_S/IBD_S bit (b1/b0, STAT1,...)
from Rx path
or Tx path
Figure-25 IB Detection
Decoding
length & content
Target code -
programming
-2
Comparison
bit error rate for a
16(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
45
respectively, as selected by the IB_IES bit (b0, INTES,...). When the
IBA_IS/IBD_IS bit (b1/b0, INTS1,...) is ‘1’, an interrupt will be reported
on INT if not masked by the IBA_IM/IBD_IM bit (b1/b0, INTM1,...).
3.5.6
errors:
errors to be counted.
ally, as determined by the CNT_MD bit (b1, ERR,...).
registers.
3.5.6.1 Automatic Error Counter Updating
updated every one second automatically.
of each one second will set the TMOV_IS bit (b0, INTTM) and induce an
interrupt reported by INT if not masked by the TMOV_IM bit (b0, GCF).
accumulated error numbers to the ERRCH and ERRCL registers and
the Error Counter will be cleared to start a new round counting. The
ERRCH and ERRCL registers should be read in the next second, other-
wise they will be overwritten.
error to be accumulated, the registers will be overflowed. The overflow is
indicated by the CNTOV_IS bit (b0, INTS2,...) and will induce an inter-
rupt reported by INT if not masked by the CNTOV_IM (b0, INTM2,...).
Figure-26.
An internal 16-bit Error Counter is used to count one of the following
• LBPV: BPV/CV detected in the receive path (line side);
• LEXZ: EXZ detected in the receive path (line side);
• LBPV + LEXZ: BPV/CV and EXZ detected in the receive path (line
• SBPV: BPV/CV detected in the transmit path (system side) (dis-
• SEXZ: EXZ detected in the transmit path (system side);
• SBPV + SEXZ: BPV/CV and EXZ detected in the transmit path
• PRBS/ARB error.
The CNT_SEL[2:0] bits (b4~2, ERR,...) select one of the above
The Error Counter is buffered. It is updated automatically or manu-
The Error Counter is accessed by reading the ERRCH and ERRCL
When the CNT_MD bit (b1, ERR,...) is ‘1’, the Error Counter is
The one-second timer uses MCLK as clock reference. The expiration
When each one second expires, the Error Counter transfers the
When the ERRCH and ERRCL registers are all ‘1’s and there is still
The process of automatic Error Counter updating is illustrated in
side);
abled in Transmit Single Rail NRZ Format mode);
(system side) (disabled in Transmit Single Rail NRZ Format
mode);
ERROR COUNTER
February 6, 2009