IDT82P2816BB IDT, Integrated Device Technology Inc, IDT82P2816BB Datasheet - Page 22

• Manufacturer Part Number: IDT82P2816BB
• Description: IC LIU T1/J1/E1 16+1CH 416-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82P2816BB

• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 1
• Voltage - Supply: 1.8V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: *
• Includes: Defect and Alarm Detection, Driver Over-Current Detection and Protection, LLOS Detection, PRBSARB / IB Detection and Generation
• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Power (watts): -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 82P2816BB

SDO / ACK / RDY
Pin Description
IDT82P2816
Name
TRST
A[10]
TMS
TCK
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
A[0]
A[1]
A[2]
A[3]
A[4]
A[5]
A[6]
A[7]
A[8]
A[9]
Output / Input
Pull-Down
Pull-up
Output
Input
Input
Input
Input
I / O
Pin No.
AE17
AF13
AC12
AD12
AE12
AF12
AD11
AE11
AE16
AF16
AD15
AE15
AF15
AC14
AD14
AE14
AF14
AD13
AE13
AF11
AE7
AD7
AE8
JTAG (per IEEE 1149.1)
SDO: Serial Data Output
In Serial microprocessor interface, this multiplex pin is used as SDO.
Data on this pin is serially clocked out of the device on the falling edge of SCLK.
ACK: Acknowledge Output (Active Low)
In Parallel Motorola microprocessor interface, this multiplex pin is used as ACK.
A low level on ACK indicates that valid information on the data bus is ready for a read opera-
tion or acknowledges the acceptance of the written data during a write operation.
RDY: Ready Output
In Parallel Intel microprocessor interface, this multiplex pin is used as RDY.
A high level on RDY reports to the microprocessor that a read/write cycle can be completed. A
low level on RDY reports that wait states must be inserted.
D[7:0]: Bi-directional Data Bus
In Parallel Motorola /Intel Non-Multiplexed microprocessor interface, these pins are the bi-
directional data bus of the microprocessor interface.
In Parallel Motorola /Intel Multiplexed microprocessor interface, these pins are the multiplexed
bi-directional address /data bus.
In Serial microprocessor interface, these pins should be connected to GNDD.
A[10:0]: Address Bus
In Parallel Motorola /Intel Non-Multiplexed microprocessor interface, these pins are the
address bus of the microprocessor interface.
In Parallel Motorola /Intel Multiplexed microprocessor interface, A[10:8], together with D[7:0],
are the address bus; while A[7:0] should be connected to GNDD.
In Serial microprocessor interface, these pins should be connected to GNDD.
TRST: JTAG Test Reset (Active Low)
A low signal on this pin resets the JTAG test port. To ensure deterministic operation of the test
logic, TMS should be held high when the signal on TRST changes from low to high.
This pin may be left unconnected when JTAG is not used.
This pin has an internal pull-down resistor.
TMS: JTAG Test Mode Select
The signal on this pin controls the JTAG test performance and is sampled on the rising edge
of TCK. To ensure deterministic operation of the test logic, TMS should be held high when the
signal on TRST changes from low to high.
This pin may be left unconnected when JTAG is not used.
This pin has an internal pull-up resistor.
TCK: JTAG Test Clock
The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising edge
of TCK and TDO is updated on the falling edge of TCK.
When TCK is idle at low state, all stored-state devices contained in the test logic shall retain
their state indefinitely.
This pin should be connected to GNDD when JTAG is not used.
16(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
22
Description
February 6, 2009