IDT82P2816BB IDT, Integrated Device Technology Inc, IDT82P2816BB Datasheet - Page 30

• Manufacturer Part Number: IDT82P2816BB
• Description: IC LIU T1/J1/E1 16+1CH 416-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82P2816BB

• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 1
• Voltage - Supply: 1.8V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: *
• Includes: Defect and Alarm Detection, Driver Over-Current Detection and Protection, LLOS Detection, PRBSARB / IB Detection and Generation
• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Power (watts): -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 82P2816BB

Table-4 Multiplex Pin Used in Transmit System Interface
3.3.2
face is in Dual Rail RZ Format mode. When the transmit system inter-
face is in other modes, the Tx Clock Recovery is bypassed
automatically.
data input on TDPn and TDNn.
3.3.3
Single Rail NRZ Format mode. When the transmit system interface is in
other modes, the Encoder is bypassed automatically.
B8ZS line code rule. In E1 mode, the data to be transmitted is encoded
by AMI or HDB3 line code rule. The line code rule is selected by the
T_CODE bit (b2, TCF1,...).
Functional Description
IDT82P2816
Note:
1. The active level on TDn, TDPn and TDNn is selected by the TD_INV bit (b3,
TCF1,...).
2. TMFn is always active high.
3. The active edge of TCLKn is selected by the TCK_ES bit (b4, TCF1,...). If TCLKn is
missing, i.e., no transition for more than 64 T1/E1 clock cycles, the TCKLOS_S bit (b3,
STAT0,...) will be set. A transition from ‘0’ to ‘1’ on the TCKLOS_S bit (b3, STAT0,...) or
any transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the TCKLOS_S bit (b3, STAT0,...) will
set the TCKLOS_IS bit (b3, INTS0,...) to ‘1’, as selected by the TCKLOS_IES bit (b3,
INTES,...). When the TCKLOS_IS bit (b3, INTS0,...) is ‘1’, an interrupt will be reported
by INT if not masked by the TCKLOS_IM bit (b3, INTM0,...).
Single Rail NRZ Format
Dual Rail NRZ Format
Dual Rail RZ Format
The Tx Clock Recovery is used only when the transmit system inter-
The Tx Clock Recovery is used to recover the clock signal from the
The Encoder is used only when the transmit system interface is in
In T1/J1 mode, the data to be transmitted is encoded by AMI or
Transmit System
Interface
T
ENCODER
X
CLOCK RECOVERY
TDn / TDPn
TDPn
TDPn
Multiplex Pin Used On Transmit System
TDn
1
1
1
TDNn / TMFn
Interface
TMFn
TDNn
TMFn
2
1
2
TCLKn / TDNn
TCLKn
TCLKn
TDNn
1
3
3
16(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
30
3.3.4
before data is transmitted:
3.3.4.1 Preset Waveform Template
template is shown in Figure-11. It is measured in the far end, as shown
in Figure-12. The J1 template is measured in the near end line side.
templates are provided according to five grades of cable length. The
selection is made by the PULS[3:0] bits (b3~0, PULS,...). In J1 applica-
tions, the PULS[3:0] bits (b3~0, PULS,...) should be set to ‘0111’. Refer
to Table-5 for details.
Figure-12 T1 Waveform Template Measurement Circuit
Note: R
IDT82P2816
The IDT82P2816 provides two ways to manipulate the pulse shape
• Preset Waveform Template;
• User-Programmable Arbitrary Waveform.
In T1/J1 applications, the waveform template meets T1.102. The T1
In T1 applications, to meet the template, five preset waveform
-0.2
-0.4
-0.6
1.2
0.8
0.6
0.4
0.2
1
0
0
WAVEFORM SHAPER
LOAD
Figure-11 DSX-1 Waveform Template
= 100 Ω + 5%
TRINGn
TTIPn
250
500
Time (ns)
750
Cable
February 6, 2009
1000
R
LOAD
1250
V
OUT