IDT82P2816BB IDT, Integrated Device Technology Inc, IDT82P2816BB Datasheet - Page 111

• Manufacturer Part Number: IDT82P2816BB
• Description: IC LIU T1/J1/E1 16+1CH 416-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82P2816BB

• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 1
• Voltage - Supply: 1.8V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: *
• Includes: Defect and Alarm Detection, Driver Over-Current Detection and Protection, LLOS Detection, PRBSARB / IB Detection and Generation
• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Power (watts): -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 82P2816BB

JM - Jitter Measurement Configuration For Channel 0 Register
JIT_PL - Positive Peak Jitter Measurement Low-Byte Register
JIT_PH - Positive Peak Jitter Measurement High-Byte Register
Address: 7E6H
Type: Read
Default Value: 00H
Address: 7E7H
Type: Read
Default Value: 00H
Address: 7E5H
Type: Read / Write
Default Value: 00H
Programming Information
IDT82P2816
7 - 0
7 - 4
3 - 0
7 - 3
Bit
Bit
Bit
2
1
0
JIT_P7
7
7
7
-
-
JIT_P[11:8]
JIT_P[7:0]
JM_STOP
JM_MD
JM_BW
Name
Name
Name
-
-
JIT_P6
6
6
-
6
-
These bits, together with the JIT_P[11:8] bits, reflect the greatest positive peak value of the demodulated jitter signal which is
measured by channel 0. They are updated automatically or manually, as determined by the JM_MD bit (b1, JM). They should be
read in the next round of jitter measurement; otherwise, they will be overwritten.
The relationship between the greatest positive peak value and the indication in these bits is:
Positive Peak = [JIT_PH, JIT_PL] / 16 (UIpp)
Reserved.
(Refer to the description of the JIT_PL register.)
Reserved.
This bit is valid only when the JM_MD bit (b1, JM) is ‘0’.
A transition from ‘0’ to ‘1’ on this bit updates the JIT_PH, JIT_PL and JIT_NH, JIT_NL registers.
This bit must be cleared before the next round.
This bit selects the jitter measurement period.
0: The period is determined manually by setting the JM_STOP bit (b2, JM). (default)
1: The period is one second automatically.
This bit selects the bandwidth of the measured jitter.
0: 10 Hz ~ 40 KHz (in T1/J1 mode) / 20 Hz ~ 100 KHz (in E1 mode). (default)
1: 8 KHz ~ 40 KHz (in T1/J1 mode) / 18 KHz ~ 100 KHz (in E1 mode).
JIT_P5
5
5
-
-
5
JIT_P4
4
4
-
-
4
16(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
111
JIT_P11
JIT_P3
3
3
-
3
Description
Description
Description
JM_STOP
JIT_P10
JIT_P2
2
2
2
JM_MD
JIT_P9
JIT_P1
1
1
1
February 6, 2009
JM_BW
JIT_P8
JIT_P0
0
0
0