UPD78F0988AGC-8BS Renesas Electronics America, UPD78F0988AGC-8BS Datasheet - Page 9

• Manufacturer Part Number: UPD78F0988AGC-8BS
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0988AGC-8BS

• Lead Free Status / Rohs Status: Supplier Unconfirmed

U13029JJ6V0UD00
Throughout
p.26
p.30
p.31
p.56
p.99
p.105
p.117
p.118
p.123
p.123
p.146
p.147
p.147
p.164
p.173
p.174
p.175
p.177
p.178
p.179
p.204
p.206
p.214
p.232
p.233
Page
Addition of 1.1 Expanded-Specification Products and Conventional Products
1.6 Pin Configuration (Top View)
3.1.2 Internal data memory space
• Addition of package
• Change of power supply voltage range as shown below.
• Change of system clock oscillation frequency (f
• Change of minimum instruction execution time
• Addition of Cautions 2 and 3 to 64-pin plastic SDIP (19.05 mm (750))
• Addition of Cautions 2 and 3 to 64-pin plastic QFP (14 x 14), 64-pin plastic LQFP (14 x 14)
Addition of description on (1) Internal high-speed RAM and (2) Internal expansion RAM
Modification of Table 5-2 Relationship Between CPU Clock and Minimum Instruction
Execution Time
Modification of Figure 5-5 Switching Between System Clock and CPU Clock
Modification of Figure 6-9 Format of Prescaler Mode Register 00
Modification of Figure 6-10 Format of Prescaler Mode Register 01
Addition of Figure 6-16 Configuration Diagram of PPG Output
Addition of Figure 6-17 PPG Output Operation Timing
Modification of Figure 7-7 Format of Timer Clock Select Register 50
Modification of Figure 7-8 Format of Timer Clock Select Register 51
Modification of Figure 7-9 Format of Timer Clock Select Register 52
Modification of Figure 8-2 Format of Inverter Timer Control Register 7
Modification of Table 9-1 Loop Detection Time of Watchdog Timer
Modification of Table 9-2 Interval Time
Modification of Figure 9-2 Format of Watchdog Timer Clock Select Register
Modification of Figure 9-4 Format of Oscillation Stabilization Time Select Register
Modification of Table 9-4 Loop Detection Time of Watchdog Timer
Modification of Table 9-5 Interval Time of Interval Timer
11.2 Configuration of A/D Converter
Addition of register figure to (2) A/D conversion result register 0 (ADCR0)
Modification of Figure 11-2 Format of A/D Converter Mode Register 0
11.5 Notes on A/D Converter
Addition of (6) Input impedance of ANI0 to ANI7 pins
Modification of Figure 12-9 Format of Baud Rate Generator Control Register 0
Modification of Figure 12-10 Format of Baud Rate Generator Control Register 1
(conventional products)
V
f
64-pin plastic LQFP (14 x 14)
X
PD780986GC-
PD780982GC(A)-
PD780986GC(A)-
PD780982GC-
DD
= 8.38 MHz
U13029JJ7V0UD00
= 4.0 to 5.5 V
f
Major Revisions in This Edition (1/2)
X
-8BS, 780983GC-
-8BS, 780988GC-
= 12 MHz (expanded-specification products only), f
V
-8BS, 780983GC(A)-
-8BS, 780988GC(A)-
DD
= 3.0 to 5.5 V (expanded-specification products), V
User’s Manual U13029EJ7V1UD
-8BS, 78F0988AGC-8BS
-8BS, 780984GC-
Description
X
-8BS, 780984GC(A)-
-8BS
) as shown below.
-8BS
X
-8BS
=8.38 MHz
DD
= 4.0 to 5.5 V
7