UPD78F0988AGC-8BS Renesas Electronics America, UPD78F0988AGC-8BS Datasheet - Page 126

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UPD78F0988AGC-8BS

Manufacturer Part Number
UPD78F0988AGC-8BS
Description
Manufacturer
Renesas Electronics America
Datasheet

Specifications of UPD78F0988AGC-8BS

Lead Free Status / Rohs Status
Supplier Unconfirmed
6.5.3 Pulse width measurement operation
0n (TM0n).
restarting the timer in synchronization with the edge of the signal input to the TI00n pin.
(1) Pulse width measurement with free-running counter and one capture register
124
It is possible to measure the pulse width of the signals input to the TI00n and TI01n pins using 16-bit timer counter
There are two measurement methods: measuring with TM0n used in free-running mode, and measuring by
Remarks 1. 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.
When 16-bit timer counter 0n (TM0n) is operated in free-running mode (see register settings in Figure 6-18),
and the edge specified by prescaler mode register 0n (PRM0n) is input to the TI00n pin, the value of TM0n is
taken into 16-bit capture/compare register 01n (CR01n) and an external interrupt request signal (INTTM01n) is
set.
The valid edge of the TI00n pin is specified by bits 4 and 5 (ES0n0, ES0n1) of PRM0n, and the rising edge, falling
edge or both edges can be selected.
When sampling is performed at the count clock cycle selected by PRM0n and the valid level of the TI00n pin
is detected twice, the first capture operation is performed, resulting in the elimination of short pulse width noise.
Remark n = 0, 1
2. n = 0, 1
TMC0n
CRC0n
Figure 6-18. Control Register Settings for Pulse Width Measurement
See Figures 6-3 to 6-6 for details.
0
0
(a) 16-bit timer mode control register 0n (TMC0n)
(b) Capture/compare control register 0n (CRC0n)
with Free-Running Counter and One Capture Register
0
0
CHAPTER 6 16-BIT TIMER/EVENT COUNTER
0
0
User’s Manual U13029EJ7V1UD
0
0
TMC0n3
0
0
TMC0n2
CRC0n2
1
1
TMC0n1
CRC0n1
0/1
0/1
OVF0n
CRC0n0
0
0
Free-running mode
CR00n as compare register
CR01n as capture register

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