UPD78F0988AGC-8BS Renesas Electronics America, UPD78F0988AGC-8BS Datasheet - Page 148

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UPD78F0988AGC-8BS

Manufacturer Part Number
UPD78F0988AGC-8BS
Description
Manufacturer
Renesas Electronics America
Datasheet

Specifications of UPD78F0988AGC-8BS

Lead Free Status / Rohs Status
Supplier Unconfirmed
146
(2) Timer clock select registers 50, 51, and 52 (TCL50, TCL51, and TCL52)
Note Expanded-specification products only.
Cautions 1. Before rewriting the data of TCL50, stop the timer operation once.
Remark f
These registers specify the count clock of 8-bit timer counters 50, 51, and 52 (TM50, TM51, and TM52) and
the valid edges of the TI50, TI51, and TI52 inputs.
TCL50, TCL51, and TCL52 are set by an 8-bit memory manipulation instruction.
RESET input clears these registers to 00H.
Figures 7-7 to 7-9 show the formats of TCL50, TCL51, and TCL52.
TCL50
Symbol
2. Be sure to clear bits 3 to 7 of TCL50 to 0.
x
: System clock oscillation frequency
TCL502 TCL501
7
0
0
0
0
0
1
1
1
1
6
0
0
0
1
1
0
0
1
1
Figure 7-7. Format of Timer Clock Select Register 50
TCL500
0
0
1
0
1
0
1
0
1
5
CHAPTER 7 8-BIT TIMER/EVENT COUNTER
f
f
f
f
f
f
X
X
X
X
X
X
Falling edge of TI50
Rising edge of TI50
/2
/2
/2
/2
/2
/2
0
4
9
3
5
7
11
User’s Manual U13029EJ7V1UD
6 MHz
1.5 MHz
375 kHz
93.7 kHz
23.4 kHz
5.85 kHz
0
3
At f
TCL502 TCL501 TCL500
X
= 12 MHz
2
Count clock selection
1
Note
0
4.19 MHz
1.05 MHz
262 kHz
65.5 kHz
16.4 kHz
4.09 kHz
At f
Address
FF71H
X
= 8.38 MHz
After reset
00H
R/W
R/W

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