UPD78F0988AGC-8BS Renesas Electronics America, UPD78F0988AGC-8BS Datasheet - Page 228

• Manufacturer Part Number: UPD78F0988AGC-8BS
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0988AGC-8BS

• Lead Free Status / Rohs Status: Supplier Unconfirmed

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(1) Transmit shift register n (TXS0n)
(2) Receive shift register n (RX0n)
(3) Receive buffer register n (RXB0n)
(4) Transmission control circuit
(5) Reception control circuit
This register is used to set the transmit data. The data written in TXS0n is transmitted as serial data.
If the data length is specified as 7 bits, bits 0 to 6 of the data written in TXS0n are transferred as transmit data.
Writing data to TXS0n starts the transmit operation.
TXS0n is written to with an 8-bit memory manipulation instruction. It cannot be read.
RESET input sets TXS0n to FFH.
Caution TXS0n must not be written to during a transmit operation. TXS0n and receive buffer register
This register is used to convert serial data input to the RxD0n pin to parallel data. When one byte of data
is received, the receive data is transferred to receive buffer register n (RXB0n).
RX0n cannot be directly manipulated by a program.
This register holds receive data. Each time one byte of data is received, new receive data is transferred from
receive shift register n (RX0n).
If the data length is specified as 7 bits, the receive data is transferred to bits 0 to 6 of RXB0n, and the MSB
of RXB0n is always set to 0.
RXB0n is read with an 8-bit memory manipulation instruction. It cannot be written to.
RESET input sets RXB0n to FFH.
Caution RXB0n and transmit shift register n (TXS0n) are allocated to the same address, and when
This circuit performs transmit operation control such as the addition of a start bit, parity bit and stop bit to data
written in transmit shift register n (TXS0n) in accordance with the contents set in asynchronous serial interface
mode register n (ASIM0n).
This circuit controls receive operations in accordance with the contents set in asynchronous serial interface
mode register n (ASIM0n). It performs error checks for parity errors, etc., during a receive operation, and if
an error is detected, sets a value in asynchronous serial interface status register n (ASIS0n) in accordance
with the error contents.
Remark n = 0, 1
n (RXB0n) are allocated to the same address, and when a read is performed, the value of
RXB0n is read.
a write is performed, the value is written to TXS0n.
CHAPTER 12 SERIAL INTERFACES UART00 AND UART01
User’s Manual U13029EJ7V1UD