UPD78F0988AGC-8BS Renesas Electronics America, UPD78F0988AGC-8BS Datasheet - Page 185
UPD78F0988AGC-8BS
Manufacturer Part Number
UPD78F0988AGC-8BS
Description
Manufacturer
Renesas Electronics America
Datasheet
1.UPD78F0988AGC-8BS.pdf
(431 pages)
Specifications of UPD78F0988AGC-8BS
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(1) Real-time output buffer register 0 (RTBL00, RTBH00)
4 bits
8 bits
Operating Mode
This register consists of two 4-bit registers that hold output data in advance.
The addresses of RTBL00 and RTBH00 are mapped individually in the special function register (SFR) area
as shown in Figure 10-2.
When specifying 4 bits
The data of both RTBL00 and RTBH00 can be read all at once regardless of which address is specified.
When specifying 8 bits 1 channel as the operation mode, data is set to both RTBL00 and RTBH00 by writing
8-bit data to either RTBL00 or RTBH00. The data of both RTBL00 and RTBH00 can be read all at once
regardless of which address is specified.
Figure 10-2 shows the configuration of RTBL00 and RTBH00, and Table 10-2 shows operations during
manipulation of RTBL00 and RTBH00.
Notes 1. Only the bits set in the real-time output port mode can be read. When a bit set in the port mode
2 channels
Table 10-2. Operation During Manipulation of Real-Time Output Buffer Register 0
1 channel
2. After setting data in the real-time output port, output data should be set in RTBL00 and RTBH00
is read, 0 is read.
by the time a real-time output trigger is generated.
Figure 10-2. Configuration of Real-Time Output Buffer Register 0
2 channels as the operation mode, data is set individually in RTBL00 and RTBH00.
Register to Be
Manipulated
CHAPTER 10 REAL-TIME OUTPUT PORT
RTBH00
RTBH00
RTBL00
RTBL00
FF84H
FF85H
User’s Manual U13029EJ7V1UD
RTBH00
Higher
4 bits
Higher 4 Bits
RTBH00
RTBH00
RTBH00
RTBH00
Reading
RTBL00
Lower
4 bits
Note 1
Lower 4 Bits
RTBL00
RTBL00
RTBL00
RTBL00
Higher 4 Bits
RTBH00
RTBH00
RTBH00
Invalid
Writing
Note 2
Lower 4 Bits
RTBL00
RTBL00
RTBL00
Invalid
183
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