UPD78F0988AGC-8BS Renesas Electronics America, UPD78F0988AGC-8BS Datasheet - Page 275

• Manufacturer Part Number: UPD78F0988AGC-8BS
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0988AGC-8BS

• Lead Free Status / Rohs Status: Supplier Unconfirmed

14.4.2 Maskable interrupt request acknowledgement operation
interrupt request mask (MK) flag is cleared to 0. A vectored interrupt request is acknowledged in the interrupt enabled
status (when the IE flag is set to 1). However, an interrupt request with a lower priority cannot be acknowledged while
an interrupt with a higher priority is being serviced (when the ISP flag is reset to 0).
in Table 14-3.
from the one assigned the highest priority by the priority specification flag. If the same priorities are specified by the
priority specification flag, the interrupt with the highest default priority is acknowledged first.
(PSW) and the program counter (PC), in that order, the IE flag is reset to 0, and the contents of the interrupt priority
specification flag of the acknowledged interrupt request are transferred to the ISP flag. In addition, the data in the
vector table determined for each interrupt request is loaded to the PC, and execution branches.
A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the corresponding
The time required to start the interrupt servicing after a maskable interrupt request has been generated is shown
For the timing of the interrupt request acknowledgement, refer to Figures 14-12 and 14-13.
When two or more maskable interrupt requests are generated at the same time, they are acknowledged starting
A pending interrupt request is acknowledged when the status in which it can be acknowledged is set.
Figure 14-11 shows the algorithm of acknowledging interrupt requests.
When a maskable interrupt request is acknowledged, the contents are saved to the stack, the program status word
To return from interrupt servicing, use the RETI instruction.
Table 14-3. Time from Generation of Maskable Interrupt Request to Servicing
Note
Remark 1 clock:
When
When
The wait time is the maximum when an interrupt request is
generated immediately before a division instruction.
PR = 0
PR = 1
CHAPTER 14 INTERRUPT FUNCTIONS
f
CPU
1
User’s Manual U13029EJ7V1UD
(f
CPU
Minimum Time
: CPU clock)
7 clocks
8 clocks
Maximum Time
32 clocks
33 clocks
Note
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