MC68EC060RC50 Freescale Semiconductor, MC68EC060RC50 Datasheet - Page 82

• Manufacturer Part Number: MC68EC060RC50
• Description: IC MPU 32BIT 50MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 50MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

4.2.2.3 DESCRIPTOR FIELD DEFINITIONS. The field definitions for the table- and page-
level descriptors are listed in alphabetical order:
CM—Cache Mode
Descriptor Address
G—Global
M—Modified
PDT—Page Descriptor Type
MOTOROLA
This field selects the cache mode and accesses serialization as follows:
Section 5 Caches provides detailed information on caching modes.
This 30-bit field, which contains the physical address of a page descriptor, is only used in
indirect descriptors.
When this bit is set, it indicates the entry is global which gives the user the option of group-
ing entries as global or nonglobal for use when PFLUSHing the ATC, and has no other
meaning. PFLUSH instruction variants that specify nonglobal entries do not invalidate glo-
bal entries, even when all other selection criteria are satisfied. If these PFLUSH variants
are not used, then system software can use this bit.
This bit identifies a page which has been written to by the processor. The MC68060 sets
the M-bit in the corresponding page descriptor before a write operation to a page for which
the M-bit is clear, except for write-protect or supervisor violations in which case the M-bit
is not set. The read portion of a locked read-modify-write access is considered a write for
updating purposes. The MC68060 never clears this bit.
This field identifies the descriptor as an invalid descriptor, a page descriptor for a resident
page, or an indirect pointer to another page descriptor.
00 = Cachable, Writethrough
01 = Cachable, Copyback
10 = Cache-Inhibited, Precise exception model
11 = Cache-Inhibited, Imprecise exception model
00 = Invalid
01 or 11 = Resident
10 = Indirect
This code indicates that the descriptor is invalid. An invalid descriptor can repre-
sent a nonresident page or a logical address range that is out of bounds. All other
bits in the descriptor are ignored. When an invalid descriptor is encountered, an
ATC entry is not created.
These codes indicate that the page is resident.
This code indicates that the descriptor is an indirect descriptor. Bits 31–2 contain
the physical address of the page descriptor. This encoding is invalid for a page
descriptor pointed to by an indirect descriptor (that is, only one level of indirection
is allowed).
M68060 USER’S MANUAL
Memory Management Unit
4-13