MC68EC060RC50 Freescale Semiconductor, MC68EC060RC50 Datasheet - Page 154

• Manufacturer Part Number: MC68EC060RC50
• Description: IC MPU 32BIT 50MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 50MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Floating-Point Unit
FSAVE on the MC68060 only generates one size frame (three long words), which creates a
significant performance benefit, and one of these three frame types. An attempt to
FRESTORE a frame format other than $00, $60, or $E0 results in a format error exception.
The format of the first long word of the MC68060 floating-point frame has changed from
that of previous M68000 microprocessors. The MC68060 frame format (bits 15–8) is a
consolidation of the version number and size format information (bits 31–16) on previous
parts. In addition, on the MC68060, this information resides in the lower word of the long
word while the upper word is used for the exception operand exponent in EXCP frames.
Therefore, FRESTORE of a frame on an MC68060 created by FSAVE on a non-MC68060
microprocessor and FRESTORE of a frame on a non-MC68060 microprocessor created by
FSAVE on an MC68060 will not guarantee a format error exception will be detected and
thus must never be attempted.
When an FSAVE is executed, the floating-point frame reflects the state of the FPU at the
time of the FSAVE. Internally, the FPU can be in the NULL, IDLE or EXCP states. Upon
reset, the FPU is in the NULL state. In the NULL state, all floating-point registers contain
nonsignaling NANs and the FPCR, FPSR, and FPIAR contain zeroes. The FPU remains in
this state until the execution of an implemented floating-point instruction (except FSAVE).
At this point, the FPU transitions from a NULL state to an IDLE state. An FRESTORE of
NULL returns the FPU to the NULL state. The EXCP state is entered as a result of either a
floating-point exception or an unsupported data type exception. V2–V0 indicates the
exception types that are associated with the EXCP state.
An FSAVE instruction always clears the internal exception status bit at the completion of
the FSAVE. An FRESTORE of EXCP may be used to place the FPU in the exception state.
The FRESTORE of an EXCP state is used in the M68060SP to provide to the user
exception handler the illusion that the M68060SP handler never existed at all. The user
exception handler is entered with the FPU in the proper exception state. The user
6-36
Frame Format
V2–V0—Exception Vector
15
$00—Null Frame
$60—Idle Frame
$E0—Exception Frame
000—BSUN
001—INEX2 | INEX1
010—DZ
011—UNFL
100—OPERR
101—OVFL
110—SNAN
111—UNSUP
Figure 6-11. Status Word Contents
FRAME FORMAT
M68060 USER’S MANUAL
8
7
0
0
0
0
3
0
V2
2
V1
1
V0
0
MOTOROLA