MC68EC060RC50 Freescale Semiconductor, MC68EC060RC50 Datasheet - Page 249

• Manufacturer Part Number: MC68EC060RC50
• Description: IC MPU 32BIT 50MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 50MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

8.3 EXCEPTION PRIORITIES
Exceptions can be divided into the five basic groups identified in Table 8-3. These groups
are defined by specific characteristics and the order in which they are handled. Table 8-3
represents the priority used for simultaneous faults, as viewed by the MC68060 hardware.
In Table 8-3, 0.0 represents the highest priority, while 4.1 is the lowest. Note that there are
shared priorities for exceptions within Group 3, since these types are mutually exclusive.
Within an MC68060 system, more than one exception can occur at the same time. The reset
exception is unique; central processing unit (CPU) reset overrides and clears all other
exceptions which may have occurred at the same time. All other exceptions are handled
according to the priority relationship defined in Table 8-3.
The method used to process exceptions in the MC68060 is similar to that found on the
MC68040 due to the restart exception model. In general, when multiple exceptions are
pending, the exception with the highest priority is processed first, and the remaining excep-
tions are regenerated when the original faulting instruction is restarted.
To clarify the exception priority within group 1, it is important to note that instruction fetch
pipeline (IFP) access errors are not recognized until the faulted portion of the instruction is
actually used (or attempted to be used). As an example, consider a “move.l (An), xxx.l”
instruction. If the source operand defined at the address contained in An is faulted, the oper-
and access error will occur. If the extension words defining the destination address are also
faulted, the IFP access error would be processed after the source operand fault. Thus, in
MOTOROLA
*
Group.Priority
Refer to Section 6 Floating-Point Unit (MC68060 Only) for details concerning floating-point instructions. For
the case of an emulated FTRAPcc instruction and a floating-point BSUN exception, the BSUN is considered
higher priority.
0.0
1.0
1.1
1.2
2.0
2.1
2.2
2.3
2.4
2.5
2.6
3.0
3.1
3.2
3.3
3.4
3.5
3.6
4.0
4.1
Reset
Address Error
Instruction Access Error
Data Access Error
A-Line Unimplemented
F-Line Unimplemented
Illegal Instruction
Privilege Violation
Unimplemented EA
Unimplemented Integer
Floating-Point Unimplemented Instruction,
Floating-Point Unsupported Data Type
Floating-Point BSUN
Zero, TRAPV, TRAPcc, TRAP #n, RTE Format
Error
Floating-Point SNAN*
Floating-Point OPERR*
Floating-Point OVFL*
Floating-Point UNFL*
Floating-Point DZ*
Floating-Point INEX*
Trace
Interrupt
Exception and Relative Priority
Table 8-3. Exception Priority Groups
*
, CHK, CHK2, Divide-by-
M68060 USER’S MANUAL
The processor aborts all processing (instruction
or exception) and does not save old context.
The processor suspends processing and saves
the processor context.
Exception processing begins before the
instruction is executed.
Exception processing begins after the initial
memory operand address is calculated, but
before instruction is executed.
Exception processing is part of instruction
execution and begins after instruction
execution.
Exception processing begins when the current
instruction is completed.
Characteristics
Exception Processing
8-17