MC68EC060RC50 Freescale Semiconductor, MC68EC060RC50 Datasheet - Page 217

• Manufacturer Part Number: MC68EC060RC50
• Description: IC MPU 32BIT 50MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 50MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Bus Operation
7-62
NOTES:
Present
Explicit
Tenure
Implicit
Explicit
Implicit
Snoop
Reset
State
Own
Own
End
Any
AM
AM
1) “N” means negated; “A” means asserted.
2) End of cycle: Whatever terminates a bus transaction whether it is normal, bus error, or retried. Note that long-word
3) Conditions C4 and F4 indicate that an alternate master has taken bus ownership without waiting for the current master
4) IBR refers to an internal bus request. The output signal BR is a registered version of IBR.
5) BTTI refers to BTT when sampled as an input.
6) SNOOP denotes the condition in which SNOOP is sampled asserted, and TT1 = 0.
7) In this state diagram, BGR is assumed always asserted; hence, bus cycles within a locked sequence are treated no
8) The processor does not require a valid acknowledge termination for snooped accesses. The only restriction is that a
bus cycles that result from a burst inhibited line transfer are considered part of that original line transfer.
to assert BTT.
differently from nonlocked bus cycles, except that the processor takes an extra BCLK period in the end tenure state
to allow for LOCK and LOCKE to negate. If BGR is negated and a locked sequence is in progress, the processor does
not relinquish the bus if BG is negated until the end of the last bus cycle in the locked sequence.
snoop cycle be performed at no more than a maximum rate of once every two BCLK cycles. This state diagram prop-
erly emulates this behavior.
Condition RSTI BG
Table 7-8. MC68060-Arbitration Protocol State Transition Conditions
A1
A2
A3
B1
B2
B3
B4
C1
C2
C3
C4
D1
D2
D3
D4
D5
E1
E2
E3
E4
E5
E6
G1
F1
F2
F3
F4
—
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
A
A
—
—
—
—
—
—
—
—
N
N
N
N
N
N
N
N
N
N
A
A
A
A
A
A
A
A
A
A
TS sampled
as an input
(TSI))
—
—
—
—
—
—
—
—
—
—
—
—
—
N
A
A
A
N
N
N
A
A
N
N
N
N
N
A
M68060 USER’S MANUAL
SNOOP
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
A
N
A
N
BTT sampled
as an input
(BTTI)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
N
A
A
A
Bus Request
Internal
(IBR)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
N
A
N
A
N
A
N
A
Progress?
Transfer
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
in
N
A
A
Cycle?
End of
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
N
A
MOTOROLA
Explicit Own
Explicit Own
Explicit Own
Explicit Own
Explicit Own
Explicit Own
Implicit Own
Implicit Own
Implicit Own
Implicit Own
Implicit Own
End Tenure
End Tenure
AM Explicit
AM Explicit
AM Explicit
AM Explicit
Next State
AM Implicit
AM Implicit
AM Implicit
AM Implicit
AM Implicit
Violation
Violation
Snoop
Snoop
Reset
Reset