MC68EC060RC50 Freescale Semiconductor, MC68EC060RC50 Datasheet - Page 310

• Manufacturer Part Number: MC68EC060RC50
• Description: IC MPU 32BIT 50MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 50MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Instruction Execution Timing
10.4 EFFECTIVE ADDRESS CALCULATION TIMES
Table 10-5 shows the number of clock cycles required to compute an instruction’s effective
address. The MC68060 address generation hardware supports the calculation of most
effective addresses within the structure of the operand execution pipeline with no additional
cycles required. The number of operand read and write cycles is shown in parentheses (r/w).
The following rules apply to any effective address calculation:
In general, the use of a memory indirect effective address adds three cycles to the instruc-
tion execution times (one cycle to process full format effective address and two cycles to
fetch the memory indirect pointer). For instructions which calculate both a source and des-
tination address (e.g., memory-to-memory moves), two effective address calculations are
performed, one for the source and another for the destination.
10.5 MOVE INSTRUCTION EXECUTION TIMES
Table 10-6 and Table 10-7 show the number of clock cycles for execution of the MOVE
instruction. The number of operand read and write cycles is shown in parentheses (r/
w).Note, if memory indirect addressing is used for a MOVE instruction, add 2(1/0) cycles for
10-14
• The size of the index register (Xi) and the scale factor (SF) do not affect the calculation
• The size of the absolute address (short, long) does not affect its calculation time. In sub-
time for the indexed addressing modes.
sequent tables, the nomenclature “(xxx).WL” is used to denote either the absolute short
{(xxx).W} or absolute long {(xxx).L} addressing modes.
([bd,An,Xn],od
([bd,An],Xn,od
(d8,PC,Xi SF) Program Counter with Index and Byte Displacement
(bd,PC,Xi SF) Program Counter with Index and Base (16-, 32-bit) Displacement
(d8,An,Xi SF) Address Register Indirect with Index and Byte Displacement
(bd,An,Xi SF) Address Register Indirect with Index and Base (16-, 32-bit) Displacement
([bd,PC,Xn],o
([bd,PC],Xn,o
(d16,PC)
(d16,An)
#<data>
(xxx).W
(xxx).L
(An)+
–(An)
(An)
Dn
An
d)
d)
)
)
Data Register Direct
Address Register Direct
Address Register Indirect
Address Register Indirect with Postincrement
Address Register Indirect with Predecrement
Address Register Indirect with Displacement
Memory Indirect Preindexed Mode
Memory Indirect Postindexed Mode
Absolute Short
Absolute Long
Program Counter with Displacement
Immediate
Program Counter Memory Indirect Preindexed Mode
Program Counter Memory Indirect Postindexed Mode
Table 10-5. Effective Address Calculation Times
Addressing Mode
M68060 USER’S MANUAL
Calculation
0(0/0)
0(0/0)
0(0/0)
3(1/0)
3(1/0)
0(0/0)
0(0/0)
0(0/0)
Time
0(0/0)
0(0/0)
0(0/0)
0(0/0)
1(0/0)
0(0/0)
0(0/0)
1(0/0)
3(1/0)
3(1/0)
MOTOROLA