MC68EC060RC50 Freescale Semiconductor, MC68EC060RC50 Datasheet - Page 140

• Manufacturer Part Number: MC68EC060RC50
• Description: IC MPU 32BIT 50MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 50MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Floating-Point Unit
the floating-point state frame is discarded, and normal execution is resumed by using the
RTE instruction.
The M68060SP not only emulates the instruction, but in addition, it ensures that if any float-
ing-point arithmetic exceptional conditions arise from the instruction emulation with the
unsupported data type instruction and if the corresponding floating-point arithmetic excep-
tion is enabled, the M68060SP restores the floating-point state frame back into the FPU in
the desired exceptional state. This effectively imitates the action of the MC68060-imple-
mented instructions.
6.5.3 Unimplemented Effective Address Exception
The unimplemented effective address exception corresponds to vector number 60, and
occurs when the processor attempts to execute a floating-point instruction that contains an
extended-precision or packed BCD immediate operand, or when the processor attempts to
execute an FMOVEM.L instruction with an immediate addressing mode to more than one
floating-point control register (FPCR, FPSR, FPIAR), or when the processor attempts an
FMOVEM.X instruction using a dynamic register list. The stack frame of type $0 is generated
when this exception is reported. The stacked PC points to the logical address of the instruc-
tion that caused the exception.
The M68060SP uses the stacked PC to point to the instruction that needs to be emulated.
The M68060SP emulates the instruction, increments the stacked PC and returns to the nor-
mal program flow.
The M68060SP not only emulates the instruction, but in addition, it ensures that if any float-
ing-point arithmetic exceptional conditions arise from the instruction emulation including the
unimplemented effective address and if the corresponding floating-point arithmetic excep-
tion is enabled, the M68060SP restores the floating-point state frame back into the FPU in
the desired exceptional state. This effectively imitates the action of the MC68060 imple-
mented instructions.
6.6 FLOATING-POINT ARITHMETIC EXCEPTIONS
The MC68060, with the aid of the M68060SP, provides the full MC68881 instruction set,
effective address, data type, and exception handling compatibility. From the perspective of
the user-supplied exception handlers, the information provided by the MC68060 or the
MC68060/M68060SP combination are consistent in that no distinction needs to be made by
the user handler between native MC68060 instructions and non-native instructions or data
types. This section discusses the operation of the MC68060, with the aid of the M68060SP,
and how information is perceived and used by the user-supplied exception handler. It is
assumed in this section that the M68060SP is already ported properly to the MC68060 sys-
tem.
6-22
M68060 USER’S MANUAL
MOTOROLA