MC68EC060RC50 Freescale Semiconductor, MC68EC060RC50 Datasheet - Page 237

• Manufacturer Part Number: MC68EC060RC50
• Description: IC MPU 32BIT 50MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 50MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

8.2.1 Access Error Exception
An access error exception occurs when a bus cycle is terminated with TEA (TA must be
negated if in MC68040 acknowledge termination mode) asserted externally or an internal
access error.
An external access error (bus error) occurs when external logic aborts a bus cycle and
asserts the TEA input signal (TA must be negated if in MC68040 acknowledge termination
mode).
the processor to begin exception processing. However, the time of reporting this bus error
is a function of the instruction type and/or memory mapping of the destination pages. For
writes that are precise (this includes certain atomic instructions like TAS and CAS and ref-
erences to pages marked noncachable precise), the occurrence of a bus error causes the
pipeline to be aborted immediately and initiates exception processing. For writes that are
imprecise (stored in push or store buffers or reference to pages marked noncachable impre-
cise), the actual bus cycle is decoupled from the instruction which generated the access. For
these types of bus errors, the exception is taken, but the state of the processor may be
advanced from the actual instruction which generated the write.
For operand read accesses generating non-line-sized references, a bus error causes the
pipeline to be immediately aborted and initiates exception processing. This is also true if a
bus error occurs on the first transfer of a line-sized transfer. For a bus error that occurs on
the second, third, or fourth transfers of a line access, the line is not allocated in the cache
and no exception is reported. If a subsequent instruction references another operand within
the given line, another system bus cycle is generated and the bus error reported at that time
(i.e., as the subsequent reference receives a bus error on its initial transfer) and the excep-
tion is then taken.
Bus errors that are signaled during instruction prefetches are deferred until the processor
attempts to execute that instruction. At that time, the bus error is signaled and exception pro-
cessing is initiated. If a bus error is encountered during an instruction prefetch cycle, but the
corresponding instruction is never executed due to a change-of-flow in the instruction
stream, the bus error is discarded.
MOTOROLA
A bus error on an operand write access always results in an access error exception, causing
• Instruction Trap
• Illegal and Unimplemented Instruction Exceptions
• Privilege Violation
• Trace
• Format Error
• Breakpoint Instruction
• Interrupt
• Reset
M68060 USER’S MANUAL
Exception Processing
8-5