EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 767

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Altera Corporation
July 2005
Jam Instructions
Each Jam statement begins with one of the instruction names listed in
Table
instructions, are reserved keywords that you cannot use as variable or
label identifiers in a Jam program.
Table 11–14
language. These keywords correspond to the state names specified in the
IEEE Std. 1149.1 JTAG specification.
Note to
(1)
BOOLEAN
CALL
CRC
DRSCAN
DRSTOP
EXIT
EXPORT
FOR
GOTO
IF
Test-Logic-Reset
Run-Test-Idle
Select-DR-Scan
Capture-DR
Shift-DR
Exit1-DR
Pause-DR
Exit2-DR
Update-DR
Select-IR-Scan
Table 11–13. Instruction Names
Table 11–14. Reserved Keywords (Part 1 of 2)
IEEE Std. 1149.1 JTAG State Names
This instruction name is an optional language extension.
11–13. The instruction names, including the names of the optional
Table
shows the state names that are reserved keywords in the Jam
11–13:
INTEGER
IRSCAN
IRSTOP
LET
NEXT
NOTE
POP
POSTDR
POSTIR
PREDR
Configuring Stratix & Stratix GX Devices
Stratix Device Handbook, Volume 2
RESET
IDLE
DRSELECT
DRCAPTURE
DRSHIFT
DREXIT1
DRPAUSE
DREXIT2
DRUPDATE
IRSELECT
Jam Reserved State Names
PREIR
PRINT
PUSH
RETURN
STATE
WAIT
VECTOR
VMAP
–
–
(1)
(1)
11–49