EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 682

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Introduction
9–12
Stratix Device Handbook, Volume 2
RX_CLK
Data invalid window before the rising edge (T
Data invalid window after the rising edge (T
RX_CLK
Data set-up time (T
Data hold time (T
Framer sampling window
Receiver skew margin (RSKM)
Table 9–6. Framer Receiver Timing Specifications
(T
duty cycle
period
)
hold
setup
Parameter
)
)
Table 9–6
Electrical Specifications
SFI-4 uses LVDS as a high-speed data transfer mechanism to implement
the SFI-4 interface.
interface, which are based on the IEEE Std. 1596.3-1996 7 specification.
For more information on the voltage specification of LVDS I/O standards
in Stratix and Stratix GX devices, see the Stratix Device Family Data Sheet
section of the Stratix Device Handbook, Volume 1 and the High-Speed
Differential I/O Interfaces in Stratix Devices chapter or the Stratix GX Device
Family Data Sheet section of the Stratix GX Device Handbook, Volume 1 and
the High-Speed Differential I/O Interfaces in Stratix Devices chapter.
lists the timing specifications for the SFI-4 framer receiver.
cq_post
cq_pre
)
)
Table 9–7
Min
300
300
600
45
lists the DC electrical characteristics for the
Value
1,608
Typ
Max
200
200
304
55
Altera Corporation
July 2005
Unit
ps
ps
ps
ps
ps
ps
ps
%