EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 334

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Enhanced PLLs
1–24
Stratix Device Handbook, Volume 2
The charge pump current directly affects the PLL bandwidth. The higher
the charge pump current, the higher the PLL bandwidth. You can choose
from a fixed set of values for the charge pump current.
the loop filter and the components that you can set via the Quartus II
software.
Figure 1–13. Loop Filter Programmable Components
Software Support
The Quartus II software provides two levels of programmable bandwidth
control. The first level allows you to enter a value for the desired
bandwidth directly into the Quartus II software using the MegaWizard
Plug-In Manager. Alternatively, you can set the bandwidth parameter in
the altpll function to the desired bandwidth. The Quartus II software
then chooses each individual bandwidth parameter to achieve the
desired setting. If designs cannot achieve the desired bandwidth setting,
the Quartus II software selects the closest achievable value. For preset
low, medium, and high bandwidth settings, the Quartus II software sets
the bandwidth as follows:
■
■
■
If you choose Auto bandwidth, the Quartus II software chooses the PLL
settings and you can get a bandwidth setting outside the 150-Khz to
2-Mhz range.
Low bandwidth is set at 150 KHz
Medium bandwidth is set at 800 KHz
High bandwidth is set at 2 Mhz
PFD
I
I
UP
DN
R
C
Figure 1–13
Altera Corporation
July 2005
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