EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 569

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Altera Corporation
July 2005
9- & 18-Bit Multipliers
You can configure each DSP block multiplier for 9 or 18 bits. A single DSP
block can support up to 8 individual 9-bit or smaller multipliers, or up to
4 individual multipliers with operand widths between 10- and 18-bits.
Figure 6–10
Figure 6–10. Simple Multiplier Mode
The multiplier operands can accept signed integers, unsigned integers, or
a combination. The signa and signb signals are dynamic and can be
registered in the DSP block. Additionally, you can register the multiplier
inputs and results independently. Pipelining the result, using the
pipeline registers in the block, increases the performance of the DSP
block.
36-Bit Multiplier
The 36-bit multiplier is a subset of the simple multiplier mode. It uses the
entire DSP block to implement one 36
multipliers are fed part of each input, as shown in
page
shiftoutb
6–21. The adder/output block adds the partial products using the
A
B
shows the simple multiplier mode.
shiftouta
ENA
ENA
D
D
CLRN
CLRN
signa
signb
Q
Q
DSP Blocks in Stratix & Stratix GX Devices
Stratix Device Handbook, Volume 2
36-bit multiplier. The four 18-bit
ENA
D
CLRN
Q
Figure 6–11 on
A
Adder Output Block
6–19