EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 418

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

DDR Memory Support Overview
Figure 3–11. Extending the OE Disable by Half-a-Clock Cycle for a Write Transaction
Note to
(1)
3–22
Stratix Device Handbook, Volume 2
from System Clock)
−90° phase shifted
The waveform reflects the software simulation result. The OE signal is an active low on the device. However, the
Quartus II software implements this signal as an active high and automatically adds an inverter before the A
register D input.
(outclock for DQS)
(from logic array)
(from logic array)
(from logic array)
(from logic array)
(outclock for DQ,
Figure
System clock
OE for DQS
Write Clock
OE for DQ
datain_h
datain_l
DQS
3–11:
DQ
90˚
Figures 3–12
DQS signals.
and
by Half
a Clock
Delay
Cycle
3–13
summarize the IOE registers used for the DQ and
Preamble
D0
D1
D0
D1
D2
D2
D3
Note (1)
Altera Corporation
D3
Postamble
June 2006
OE