EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 477

• Manufacturer Part Number: EP1S40B956C5
• Description: IC STRATIX FPGA 40K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40B956C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Altera Corporation
July 2005
PCML
The PCML I/O standard is a differential high-speed, low-power I/O
interface standard used in applications such as networking and
telecommunications. The standard requires a 3.3-V V
standard achieves better performance and consumes less power than the
LVPECL I/O standard. The PCML standard is similar to LVPECL, but
PCML has a reduced voltage swing, which allows for a faster switching
time and lower power consumption.See the Stratix Device Family Data
Sheet section of the Stratix Device Handbook, Volume 1 for the PCML
signaling characteristics.
Differential HSTL (Class I & II)
The differential HSTL I/O standard is used for applications designed to
operate in the 0.0- to 1.5-V HSTL logic switching range such as quad data
rate (QDR) memory clock interfaces. The differential HSTL specification
is the same as the single ended HSTL specification. The standard specifies
an input voltage range of – 0.3 V V
HSTL I/O standard is only available on the input and output clocks. See
the Stratix Device Family Data Sheet section of the Stratix Device Handbook,
Volume 1 for the HSTL signaling characteristics
Differential SSTL-2 (Class I & II)
The differential SSTL-2 I/O standard is a 2.5-V memory bus standard
used for applications such as high-speed double data rate (DDR) SDRAM
interfaces. This standard defines the input and output specifications for
devices that operate in the SSTL-2 logic switching range of 0.0 to 2.5 V.
This standard improves operation in conditions where a bus must be
isolated from large stubs. The SSTL-2 standard specifies an input voltage
range of – 0.3 V V
and output levels. The differential SSTL-2 I/O standard is only available
on output clocks. See the Stratix Device Family Data Sheet section of the
Stratix Device Handbook, Volume 1 for the SSTL-2 signaling characteristics.
Stratix Differential I/O Pin Location
The differential I/O pins are located on the I/O banks on the right and
left side of the Stratix device.
device high-speed differential I/O buffers. When the I/O pins in the I/O
banks that support differential I/O standards are not used for high-speed
I
High-Speed Differential I/O Interfaces in Stratix Devices
V
CCIO
+ 0.3 V. Stratix devices support both input
Table 5–1
I
V
Stratix Device Handbook, Volume 2
shows the location of the Stratix
CCIO
+ 0.3 V. The differential
CCIO
. The PCML I/O
5–5