EP1S40B956C5 Altera, EP1S40B956C5 Datasheet - Page 616

IC STRATIX FPGA 40K LE 956-BGA

EP1S40B956C5

Manufacturer Part Number
EP1S40B956C5
Description
IC STRATIX FPGA 40K LE 956-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S40B956C5

Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
683
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
956-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-

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0
Infinite Impulse Response (IIR) Filters
7–38
Stratix Device Handbook, Volume 2
The first DSP block in
adder mode, and the second DSP block is in the four-multipliers adder
mode. For an 18-bit input to the IIR filter, each biquad requires five
multipliers and five adders (two DSP blocks). One of the adders is
implemented using logic elements. Cascading several biquads together
can implement more complex, higher order IIR filters. It is possible to
insert registers in between the biquad stages to improve the performance.
Figure 7–23
biquads in three DSP blocks.
Figure 7–23. Two Cascaded Biquads
a
x[n]
a
a
a
b
b
b
b
a
a
10
20
21
11
12
11
12
21
22
22
shows a 4
Four-multipliers
adder mode
Four-multipliers
adder mode
Two-multipliers
adder mode
th
Figure 7–22
order IIR filter realized using two cascaded
block 3
block 1
block 2
DSP
DSP
DSP
is configured in the two-multipliers
Altera Corporation
September 2004
Second
biquad
biquad
First
y[n]

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