MT48H8M16LFB4-75 IT:J Micron Technology Inc, MT48H8M16LFB4-75 IT:J Datasheet - Page 30

• Manufacturer Part Number: MT48H8M16LFB4-75 IT:J
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H8M16LFB4-75 IT:J

• Organization: 8Mx16
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 8/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 70mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

DEEP POWER-DOWN (DPD)
Operations
Truth Tables
Table 16:
PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac
sdr_mobile_sdram_cmd_op_timing_dia_fr10_08__3.fm - Rev. E 4/09 EN
Current State
Any
Idle
Row active
Read
(auto precharge disabled)
Write
(auto precharge disabled)
Truth Table – Current State Bank n, Command to Bank n
Notes 1–6 apply to all parameters in this table; notes appear below table
Notes:
The DEEP POWER-DOWN (DPD) command is used to enter deep power-down mode,
achieving maximum power reduction by eliminating the power to the memory array. To
enter DPD, all banks must be idle. While CKE is LOW, hold CS# and WE# LOW, and hold
RAS# and CAS# HIGH at the rising edge of the clock. To exit DPD, assert CKE HIGH.
1. This table applies when CKE
2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank
3. Current state definitions:
4. The states listed below must not be interrupted by a command issued to the same bank.
CS#
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
after
and the commands shown can be issued to that bank when in that state. Exceptions are
covered in the notes below.
COMMAND INHIBIT or NOP commands, or supported commands to the other bank should
be issued on any clock edge occurring during these states. Supported commands to any
Idle:
Row active:
Read:
Write:
RAS# CAS#
t
H
H
H
H
H
H
H
H
H
XSR has been met (if the previous state was self refresh).
X
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
X
L
L
L
L
L
L
L
L
The bank has been precharged, and
A row in the bank has been activated, and
bursts/accesses and no register accesses are in progress.
not yet terminated or been terminated.
A WRITE burst has been initiated, with auto precharge disabled, and has
not yet terminated or been terminated.
A READ burst has been initiated, with auto precharge disabled, and has
WE#
X
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM
COMMAND INHIBIT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
ACTIVE (select and activate row)
AUTO REFRESH
LOAD MODE REGISTER
PRECHARGE
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE (deactivate row in bank or banks)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE (truncate READ burst, start PRECHARGE)
BURST TERMINATE
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE (truncate WRITE burst, start PRECHARGE)
BURST TERMINATE
n-1
30
was HIGH and CKE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Command/Action
n
is HIGH (see Table 18 on page 34) and
t
RP has been met.
t
RCD has been met. No data
©2008 Micron Technology, Inc. All rights reserved.
Operations
Notes
9, 10
9, 10
11
10
10
10
10
10
10
7
7
8
8
8