MT48H8M16LFB4-75 IT:J Micron Technology Inc, MT48H8M16LFB4-75 IT:J Datasheet - Page 10

• Manufacturer Part Number: MT48H8M16LFB4-75 IT:J
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48H8M16LFB4-75 IT:J

• Organization: 8Mx16
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 8/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 70mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / Rohs Status: Compliant

Ball Descriptions
Table 3:
PDF: 09005aef832ff1ea/Source: 09005aef832ff1ac
128mb_mobile_sdram_y35m__2.fm - Rev. E 4/09 EN
54-Ball VFBGA 90-Ball VFBGA
G2, H9, G3, H1,
A2, B1, B2, C1,
C2, D1, D2, E1,
E9, D8, D9, C8,
C9, B8, B9, A8
H2, H3, J2, J3,
J7, J8, H8, H7
F7, F8, F9
G7, G8
E8, F1
G9
F2
F3
VFBGA Ball Descriptions
P1, M2, M3, L2,
L8, M7, M8, P9,
H1, G3, G2, G1,
H9, G7, J3, H2,
E2, D3, D2, B1,
C2, A1, C3, A2,
A8, C7, A9, C8,
B9, D8, D7, E8,
R2, N3, R1, N2,
N8, R9, N7, R8
F3, F7, G9, G8
F2, F8, K1, K9
K7, J9, K8
J7, H8
J1
J2
J8
CAS#, RAS#,
DQM[3:0]
BA0, BA1
DQ[15:0]
DQ[31:0]
Symbol
(54-ball)
(90-ball)
(54-ball)
(90-ball)
LDQM,
A[11:0]
UDQM
WE#
CKE
CLK
CS#
Input
Input
Input
Input
Input
Input
Input
Type
I/O
128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM
Clock: CLK is driven by the system clock. All SDRAM input signals
are sampled on the positive edge of CLK. CLK also increments
the internal burst counter and controls the output registers.
Clock enable: CKE activates (HIGH) and deactivates (LOW) the
CLK signal. Deactivating the clock provides precharge power-
down and SELF REFRESH operation (all banks idle), active power-
down (row active in any bank), deep power-down (all banks
idle), or CLOCK SUSPEND operation (burst/access in progress).
CKE is synchronous except after the device enters power-down
and self refresh modes, where CKE becomes asynchronous until
after exiting the same mode. The input buffers, including CLK,
are disabled during power-down and self refresh modes,
providing low standby power.
Chip select: CS# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when CS# is registered HIGH. CS# provides for external
bank selection on systems with multiple banks. CS# is considered
part of the command code.
Command inputs: RAS#, CAS#, and WE# (along with CS#) define
the command being entered.
Input/Output mask: DQM is sampled HIGH and is an input mask
signal for write accesses and an output enable signal for read
accesses. Input data is masked during a WRITE cycle. The output
buffers are placed in a High-Z state (2-clock latency) during a
READ cycle. For the x16, LDQM corresponds to DQ[7:0] and
UDQM corresponds to DQ[16:8]. For the x32, DQM0 corresponds
to DQ[7:0], DQM1 corresponds to DQ[15:8], DQM2 corresponds
to DQ[23:16], and DQM3 corresponds to DQ[31:24]. DQM[3:0]
(or LDQM and UDQM if x16) are considered same state when
referenced as DQM.
Bank address input(s): BA0 and BA1 define to which bank the
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied. BA0 and BA1 become “Don’t Care” when registering an
ALL BANK PRECHARGE (A10 HIGH).
Address inputs: Addresses are sampled during the ACTIVE
command (row) and READ/WRITE command (column; with A10
defining auto precharge) to select one location out of the
memory array in the respective bank. A10 is sampled during a
PRECHARGE command to determine whether all banks are to be
precharged (A10 HIGH) or bank selected by BA0, BA1. The
address inputs also provide the op-code during a LOAD MODE
REGISTER command.
Data input/output: Data bus.
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Description
©2008 Micron Technology, Inc. All rights reserved.
Ball Descriptions