EW80314GS Q 099 Intel, EW80314GS Q 099 Datasheet - Page 38

• Manufacturer Part Number: EW80314GS Q 099
• Manufacturer: Intel

Specifications of EW80314GS Q 099

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Documentation Changes
7.
Issue:
Affected Docs: Intel
8.
Issue:
Affected Docs: Intel
9.
Issue:
Affected Docs: Intel
10.
Issue:
Affected Docs: Intel
38
Various ball map diagram signals are not correct
In section 3.1.18, Figure 3, the following ball labels are incorrect:
SDRAM feedback clock length
The note in Section 7.3 (bottom of page 54) specifies to design the SD_CKFBI trace length to
match the average clock length plus the average DQS length. The SD_CKFBI trace should be
3 inches.
PCI Interrupt Assertion register IRP_PIA added
Current documentation omits a register required to interrupt the host in a host bus adaptor configu-
ration. The register described below is now a valid register of the PCI/X block (offset 0x190) and is
present in all steppings. For further information on the use of this register for host messaging and
interrupts, refer to the application note, Host Bus Adapter Considerations with the Intel
Processor Companion Chip (order number 274048).
PFAB_MEM32[11:0] field description should be reserved
In Section 3.18.5.25, Table 157, bit field [11:0] of the PFAB_MEM32 register should be reserved.
IRP_PIA (PCI Interrupt Assertion)
Register Offset: 0x190
•
•
•
•
31:29
27:0
C12 is documented as SD_DQS[35]. It should be SD_DQ[35].
C14 is documented as SD_DQ[14]. It should be SD_DQS[14].
C16 and C17 are both documented as SD_DQ[37]. C16 should be SD_DQ[37], and C17
should be SD_DQ[32].
AU33 is documented as NT[6]. It should be INT[6].
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Bit
28
80314 I/O Processor Companion Chip Datasheet (273757-001)
80314 I/O Processor Companion Chip Design Guide (273758-001)
80314 I/O Processor Companion Chip Developer’s Manual
80314 I/O Processor Companion Chip Developer’s Manual
Default
–
0
–
Intel
Reserved
Writing a 1 asserts PCI interrupt INTA. Clearing the bit de-asserts the interrupt.
Note the following requirements for this bit to function:
Reserved
®
• The PCI block must be configured with RST_DIR = 0
• IRP_CFG_CTL (0x180) INTA_TYPE field must be 01b
• IRP_CFG_CTL (0x180) LOC_INT_DEST must be 01b
• IRP_CFG_CTL (0x180) INTA_DIR must be 1b
80314 I/O Processor Companion Chip Specification Update
Description
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80314 I/O