EW80314GS Q 099 Intel, EW80314GS Q 099 Datasheet - Page 30

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EW80314GS Q 099

Manufacturer Part Number
EW80314GS Q 099
Description
Manufacturer
Intel
Datasheet

Specifications of EW80314GS Q 099

Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
Specification Changes
8.
Issue:
Affected Docs: Intel
9.
Issue:
Affected Docs: Intel
10.
Issue:
Affected Docs: Intel
30
MPIC interrupt mapping change
The MPIC interrupt mapping of the Ethernet and UARTs was changed from the A0 to B0 stepping
to provide separate interrupts for the UARTs and GigE ports. In addition, the B0 stepping maps
only the Misc. interrupt to I2C. The output of the interrupt pending register (IPR) is an interrupt
number permanently assigned to each interrupt source. The following entries from Table 461 of the
Intel
Input hold time on CPU interface
The current input hold time maximum specifications (T
Intel
XScale
to be changed to 2.2 ns starting with the B1 stepping and is not expected to impact design
guidelines.
Reset slew rate for battery-backup entry
The slew rate for the assertion of reset (P1_RST#, P2_RST#, SFN_RST#) must be no slower than
20 nS/V when entering DDR battery-backup mode, so a reset slew-rate specification is being
added:
Intel
MPIC Interrupt
Flag Number
®
(Decimal)
®
®
®
®
®
80314 I/O Processor Companion Chip Design Guide are to be changed from A0 to B0.
80314 I/O Processor Companion Chip Developer’s Manual
80314 I/O Processor Companion Chip is 0.6 ns (see Table 38, “AC Specifications for Intel
80314 I/O Processor Companion Chip Datasheet
80314 I/O Processor Companion Chip Design Guide
80314 I/O Processor Companion Chip Datasheet
®
13
14
15
16
21
Tsrst
Microprocessor Interface” in section 4.4.5 of the datasheet). This specification is planned
20 nS/V maximum
Processor Companion Chip Developer’s
(currently shown in the Intel
Misc. (I2C, UART0, UART1 combined)
Intel
GigE (ports 0 and 1 combined)
®
80314 I/O Processor Companion Chip Specification Update
Manual)
INT[13]
INT[14]
INT[15]
A0
®
80314 I/O
Source
IH1
and T
IH2
) for the CPU interface of the
GigE Port 0
GigE Port 1
UART0
UART1
I2C
B0

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