EW80314GS Q 099 Intel, EW80314GS Q 099 Datasheet - Page 31

• Manufacturer Part Number: EW80314GS Q 099
• Manufacturer: Intel

Specifications of EW80314GS Q 099

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

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Affected Docs: Intel
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Affected Docs: Intel
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Intel
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80314 I/O Processor Companion Chip Specification Update
Reset input hold time for HBA battery-backup entry
The PCI/X reset input hold time parameters for the 80314, Tih2 and Tih3, are being changed from
0 to -600 pS. This change is applicable only to the assertion edge when using reset to enter
SDRAM standby mode.
In an HBA configuration, the host bus PCI/X reset (P1_RST# or P2_RST#) to the 80314 becomes
the primary reset input to the 80314. In this configuration, SFN_RST# is no longer a reset input
(disabled). During power failure, an HBA voltage monitor circuit must be able to assert the
Px_RST# input pin to the 80314 to enter battery-backup mode. This must be done, however,
without resetting the host bus. The isolation of the power-failure reset from the host bus can be
achieved by inserting an OR gate between the host bus Px_RST# signal and the 80314 Px_RST#
pin. Changing Tih2 and Tih3 to -600 pS enables selection of a gate to achieve this and still meet
timing requirements for the PCI-X initialization sequence.
Intel
Removal of shadow registers
Starting with the B0 stepping, the following shadow registers are de-featured:
Single Data Rate SDRAM is not supported
The 80314 memory controller supports Double Data Rate (DDR) SDRAM. Single Data Rate
(SDR) SDRAM is not supported.
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P_CSR_SHADOW
P_MISC1_SHADOW
P_MISC2_SHADOW
SERR_STAT_SHADOW
P_PCI/X_C_SHADOW
P_PCI/X_S_SHADOW
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80314 I/O Processor Companion Chip Design Guide
80314 I/O Processor Companion Chip Datasheet
80314 I/O Processor Companion Chip Design Guide
80314 I/O Processor Companion Chip Developer’s Manual
Specification Changes
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