EW80314GS Q 099 Intel, EW80314GS Q 099 Datasheet
EW80314GS Q 099
Specifications of EW80314GS Q 099
Related parts for EW80314GS Q 099
EW80314GS Q 099 Summary of contents
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... Companion Chip Specification Update July 2005 ® Notice: The Intel 80314 I/O Processor Companion Chip may contain design defects or errors known as errata that may cause the product to deviate from published specifications. Current characterized errata are documented in this specification update. Order Number: 273759-010US ...
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... Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems nuclear facility applications. Intel may make changes to specifications and product descriptions at any time, without notice. ...
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... Contents Revision History ......................................................................................... 5 Preface....................................................................................................... 7 Summary Table of Changes....................................................................... 8 Identification Information.......................................................................... 14 Errata ....................................................................................................... 16 Specification Changes ............................................................................. 28 Specification Clarifications ....................................................................... 32 Documentation Changes ......................................................................... 37 ® Intel 80314 I/O Processor Companion Chip Specification Update 3 ...
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... THIS PAGE INTENTIONALLY LEFT BLANK 4 ® Intel 80314 I/O Processor Companion Chip Specification Update ...
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... July 2005 April 2005 March 2005 August 2004 July 2004 May 2004 April 2004 ® Intel 80314 I/O Processor Companion Chip Specification Update 010 • Added Documentation Changes • Corrected Port_Arb settings in Erratum include a setting of 11b as fixed in the B1 stepping. • Corrected Errata 43 to read “ ...
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... Updated Documentation Changes section, added specific references and added documentation change 5 002 • Updated Specification Changes, Specification Clarifications and Documentation Changes sections with correct formats and sub-sections • Updated this specification update document with Intel template changes 001 Initial release. ® Intel ...
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... I/O Processor Companion Chip Design Guide Nomenclature Errata are design defects or errors. These may cause the behavior of the Intel Processor Companion Chip to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices ...
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... Summary Table of Changes The following table indicates the errata, specification changes, specification clarifications, or documentation changes which apply to the Intel fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. This table uses the following ...
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... LS_VECTOR field of the VECTORx registers may report 17 Fixed incorrect value 0 A VECTORx read of 0xFF does not always mean that no 17 Fixed interrupts are pending Two Intel XScale® cores cannot be the target of a single 18 Fixed interrupt Fix DMA channel may require reset following SFN TEA errors ...
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... Bit[0] of the Revision ID field of the PCI Class Override 26 Fixed Register is stuck Fix GPIO[7:0] pins are driven on reset Fix External PCI/X DMA to SRAM sync packet Possible lost interrupt due to read/write of aliased IACKx Fix registers ® Intel 80314 I/O Processor Companion Chip Specification Update Errata ...
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... Intel 80314 I/O Processor Companion Chip Specification Update Page Specification Changes Intel® 80314 I/O Processor Companion Chip does not support transparent 28 mode operation 28 SFN buffer sizes for PCI-X and SDRAM interfaces Only two REQ/GNT pairs are available with the internal arbiter when the ...
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... Requirements for booting to other than an 8-bit PBI width 33 Time-outs may result in data overwrites The Intel® 80314 I/O Processor Companion Chip configuration retry 33 mechanism requires the use of SEEROM Intel® 80314 I/O Processor Companion Chip is capable but 33 tested only Maximum I2C memory 33 ...
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... Intel 80314 I/O Processor Companion Chip Specification Update Page Documentation Changes PCI-X Bridge Status Register (Embedded Mode) (PE_PCI/X _S) has 37 incorrect values for default bus and function numbers 37 PFAB_CSR Register is described incorrectly 37 Removed and moved to Errata #39 ...
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... Identification Information Identification Information Markings Topside Markings (A-0 Example) 14 ® Intel 80314 I/O Processor Companion Chip Specification Update ...
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... B-1 GW80314GN B-1 GW80314GS B-1 GW80314GS B-1 GW80314GS Device ID Registers Device and Stepping 80314 A-0 80314 B-0 80314 B-1 ® Intel 80314 I/O Processor Companion Chip Specification Update QDF (Q)/ Specification Number (SL) Q468 Q469 Q471 Q472 Q738 Q739 SL7DC Q740 Q741 SL7DD ...
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... Errata 1. PE_CSR[R_TA] status bit may not be set ® Problem: When the Intel configured for embedded mode and the destination is one of the PCI-X interfaces, when the 80314 masters a Mem_Read_Mult command for which it receives target abort, the PE_CSR[R_TA] status bit is not set. Implication: This behavior prevents the assertion of an interrupt that may be mapped to this bit ...
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... INTs are pending. Workaround: When a spurious vector is reported, software must read the register indicated by the LS_VECTOR field in the VECTORx register to determine whether the INT is truly spurious Status: Fixed ® Intel 80314 I/O Processor Companion Chip Specification Update Errata 17 ...
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... Problem: Only one interrupt output may be selected in the SEL_OUT field of the control registers for each interrupt source. Implication: When two Intel XScale an interrupt. Workaround: When both cores require notification of an interrupt, one core must be specified as the target and must use an application-specific mechanism to report the interrupt to the other core. Examples are shared memory, use of the doorbell interrupt in the MPIC, and so on ...
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... Implication: SRAM should not be used. Workaround: Use SDRAM. Status: Fixed 16. Multi-byte writes are not supported on the Intel Companion Chip Problem: When performing a multi-byte write writes. The I C EEPROM requires at least 10 ms before accepting the next write. The I provide enough time for one byte to complete before starting the next. ...
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... There is an issue with the way the synchronization is done between the SFN and SDRAM clock domains that may impact performance. Implication: Performance through SDRAM (one PCI bus writing and one reading) is impacted by approxi- mately 5%. Workaround: None Status: Fixed 20 ® Intel 80314 I/O Processor Companion Chip Specification Update ...
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... The PCI-X 1.0a specification defines these bits as reserved. Workaround: None Status: Fixed 26. PFAB_CSR TEA bit is not functional Problem: The PFAB_CSR register time-out bit located at bit 28 does not get set on a time-out. Implication: None Workaround: None Status: Fixed ® Intel 80314 I/O Processor Companion Chip Specification Update Errata 21 ...
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... Plugging the 80314 into a 33 MHz 5 V PCI bus draws excessive current, leading to damage and/or device failure. Workaround: None. Do not design the 80314 into bus/backplane. Also, do not connect 5-volt PCI devices to either of the FL PCI interfaces. Status: No Fix 22 ® Intel 80314 I/O Processor Companion Chip Specification Update ...
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... Use only PORT_ARB 00*, 01 settings for B1 stepping. Use only 01 setting for A0/B0 steppings. Note: Refer to Errata 33 on the implication of using PORT_ARB = 00. Refer to Specification Clarification 17 on the implication of using PORT_ARB = 01. Status: No Fix ® Intel 80314 I/O Processor Companion Chip Specification Update Errata 23 ...
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... Ensure entire frame is buffered in FIFO prior to the start of transmission by setting the “Start sending threshold” TX Thresholds register (Offset: 0x230/0x630) >= the frame size. See Table 376 of the Intel Some applications can use frames larger than 2K without occurrence of over-run and incorrect incrementing of TUND. ...
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... Implication: A0/B0 steppings are restricted to using a PORT_ARB setting of 01*. This setting gives SDRAM priority to the SFN and may hold off Intel XScale Workaround: Use only the 01 PORT_ARB settings for A0/B0 steppings. Use only 00*, 01*, 11 for B1 stepping. ...
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... SFN fabric to SDRAM before being accessed by the Intel XScale the second memory port. For more complete information on when sync packets are needed see section 4.2.6 of the Intel 80314 I/O Processor Companion Chip Developer’s Manual (273756). Also see the white paper ...
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... PCI/X block to the SRAM is flushed from the SFN fabric to SRAM before being accessed by the Intel XScale Section 4.2.6 of the Intel Also see the white paper entitled Sync Packet Architectural Usage for the Intel Processor Companion Chip (302325). Implication: Since the PCI/X to SRAM sync packet does not work properly, external DMA must transfer data only to/from SDRAM (PCI/X to SDRAM sync packets work) ...
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... SFN buffer sizes for PCI-X and SDRAM interfaces Issue: Starting with the B0 stepping of the Intel size in both the PCI-X and SDRAM interfaces is increased from 256 bytes to 1024 bytes (default). External storage traffic patterns from PCI-X to PCI-X or PCI-X to SDRAM can achieve higher throughput ...
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... Additional nominal and maximum power data; correction of power dissipation values Issue: Table 29 (in Section 4.1 of the Intel list nominal and maximum power consumption for each voltage rail. The following entries are to be added to Table 29: Symbol PVCC33 3.3 V supply power PVCC25 2.5 V supply power PVCC12 1 ...
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... Issue: The current input hold time maximum specifications (T ® Intel 80314 I/O Processor Companion Chip is 0.6 ns (see Table 38, “AC Specifications for Intel ® XScale Microprocessor Interface” in section 4.4.5 of the datasheet). This specification is planned to be changed to 2.2 ns starting with the B1 stepping and is not expected to impact design guidelines. ® ...
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... Single Data Rate SDRAM is not supported Issue: The 80314 memory controller supports Double Data Rate (DDR) SDRAM. Single Data Rate (SDR) SDRAM is not supported. ® Affected Docs: Intel 80314 I/O Processor Companion Chip Developer’s Manual ® Intel 80314 I/O Processor Companion Chip Specification Update ...
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... Multi-bit ECC error behaviors Issue: When a multi-bit ECC error occurs in the second data phase of a burst write from the Intel XScale processor into the 80314, the 80314 incorrectly forward the write to the destination. The correct function is to disable the byte enables when forwarding a write transaction where the ECC was detected ...
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... Maximum I C memory Issue: The maximum supported size for data in EEPROM is 255 bytes (byte count field 0x00FE). ® Affected Docs: Intel 80314 I/O Processor Companion Chip Developer’s Manual 10. Proper handling of Gigabit Ethernet WAIT condition Issue: Heavy Ethernet and SFN traffic resulting in slow interrupt response and/or insufficient data buffer capacity may fail to free up Gigabit Ethernet RX buffers (receive queue) fast enough, triggering a WAIT condition (data in FIFO but no buffers available) ...
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... CIU and DMA. One implication is that the DMA destination port can conveniently be used to direct DMA to PCI/X transfers to PCI1 or PCI2 memory space important to remember that PCI/X memory access directly from the Intel XScale (without DMA/XOR, 32-bit addresses) still needs a configured CIU BAR (and its LUT) to route the access through to the desired PCI/X port with the correct translated address. ® ...
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... The solution for PORT_ARB = 01 mode involves inserting a read between the SDRAM write and the PCI/X agent writes. This works because ordering rules require posted writes to complete before reads, and the Intel XScale is delayed. Be careful that the read is to uncacheable/unbufferable SDRAM, so that the Intel ® XScale port is forced to fetch data from SDRAM ...
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... This behavior does not apply to operation in PCI-X mode. Host address map / BAR settings for the Intel embedded HBA configuration must not hit the end of physical memory. Inbound transactions are expected to be comprised of mainly command and status operations, with host data transfers being handled through the internal DMA of the Intel ® ...
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... GPIO Data Register offset is documented as 0x5A0 (Table 458). It should be 0xA0. • GPIO Control Register offset is documented as 0x5A4 (Table 459). It should 0xA4. ® Affected Docs: Intel 80314 I/O Processor Companion Chip Developer’s Manual ® Intel 80314 I/O Processor Companion Chip Specification Update ...
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... The register described below is now a valid register of the PCI/X block (offset 0x190) and is present in all steppings. For further information on the use of this register for host messaging and interrupts, refer to the application note, Host Bus Adapter Considerations with the Intel Processor Companion Chip (order number 274048). ...
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... The Intel 80314 I/O Processor Companion Chip Developer’s Manual refers to UARTs 1 and 2, while the datasheet refers to UARTs 0 and 1. Thus, the UART signals in the Intel Processor Companion Chip Developer’s Manual (in bit 0 of Table 459, “GPIO Control (GPIO_CNTRL)”, in Section 11.4) should be re-labeled as follows (in both the “Pin Name” and “ ...
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... PCI/X initialization sequence Issue: The frequency tolerances listed in Table 46 in the Intel Developer’s Manual (Section 3.11.1) are misleading, resulting in an incorrect PCI/X CAP#[1,0] selection for the desired initialization sequence. For example, Px_RSTDIR = 1 and PCI/X CAP#[1,1] cause the PCI-X 133 MHz initialization sequence to be driven by the 80314. Thus, a device expecting 100 MHz operation with PCI/X CAP#[1,1] receives the incorrect initialization sequence (PCI/X 133) ...
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... Signal Listing Corrections Issue: Incorrect signal listings are given in Section 3.1.18 of the Intel Chip Datasheet, Figures 3 and 4, Tables 20 and 21: • In Table 21, “1025-Lead HSBGA Package”, the Alphabetical Signal Listing has some incorrect entries: — Page 56—AN29 is documented as VCC_PC. It should be VCC_CORE. — Page 56—Signals AP29, AP30, AP31 are missing from the table (VCC_PC type signals). ...
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... I/O Processor Companion Chip Design Guide 18. GPIO attribute reversal Issue: Table 458 of the Intel reverses the attributes for bits[15:8] and bits[31:24] of the GPIO_DATA register (0x5A0). The correct attributes for bits[15:8] are RW, and the correct attributes for bits[31:24] are RO. ® Affected Docs: Intel 80314 I/O Processor Companion Chip Developer’ ...
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... SRAM Integrated GigE with descriptor in SRAM and S5b data in SDRAM * Please refer to Specification Clarification #15 in the Intel® 80314 I/O Processor Companion Chip Specification Update . PCIX cannot be the destination (second destination port sync packet ® Affected Docs: Intel 80314 I/O Processor Companion Chip Developer’s Manual ® ...
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... Documentation Changes THIS PAGE INTENTIONALLY LEFT BLANK 44 ® Intel 80314 I/O Processor Companion Chip Specification Update ...