EW80314GS Q 099 Intel, EW80314GS Q 099 Datasheet - Page 25

• Manufacturer Part Number: EW80314GS Q 099
• Manufacturer: Intel

Specifications of EW80314GS Q 099

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

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Intel
®
80314 I/O Processor Companion Chip Specification Update
Note: Refer to Specification Clarification
Testing SDRAM single-bit ECC errors with 64-bit writes
Single-bit error occurrences/corrections resulting from soft insertion of an ECC syndrome (to test
ECC) are not reported as expected for 64-bit writes (with 64- or 32-bit reads) to un-cacheable/un-
bufferable memory. The inserted error is detected and corrected properly, but the occurrence is not
noted in the SD_ECC_STATUS nor the SD_ECC_ADDR1/SD_ECC_ADDR2 registers for 64-bit
writes. 64-bit writes to un-cacheable/un-bufferable memory are split into two 32-bit
read-modify-write (RMW) transactions. The first 32-bit RMW inserts the syndrome, the second
RMW corrects it, but no corrected error is reported.
This behavior impacts only the testing of single-bit ECC errors for 64-bit writes (soft-inserted
single-bit errors). The inserted error is detected and corrected properly but is not reported. Hard
single-bit ECC errors are detected, corrected, and reported properly.
Insertion/testing of single bit ECC errors must either:
No Fix
INT_DIS read-only field prevents enabling INTx# assertion
Both the MWI_EN and INT_DIS bits must be read/write. The INT_DIS bit enables/disables the
ability of the interface to assert INTx#. Since this bit is cleared by default and is read-only, you
cannot write to the INT_DIS field to enable assertion of INTx#.
In Table 91 in Section 3.18.3.2 of the Intel
Manual (273756-002), the register drawing shows the following incorrect bit labels:
For the A0 stepping, you cannot write to the INT_DIS field to enable assertion of INTx#
None
Fixed
80200 lockup for Port Arbitration settings 11
Concurrent Intel XScale
memory region can result in 80200 lockup for port arbitration settings 11.
A0/B0 steppings are restricted to using a PORT_ARB setting of 01*. This setting gives SDRAM
priority to the SFN and may hold off Intel XScale
Use only the 01 PORT_ARB settings for A0/B0 steppings. Use only 00*, 01*, 11 for B1 stepping.
33
Fixed
1. Use cacheable/bufferable access
2. Use 32-bit accesses
•
•
on implications of using PORT_ARB = 00.
The MWI_EN bit (bit[4]) is read/write but is documented as read-only.
The INT_DIS bit (bit[10]) is read-only but is documented as read/write.
®
core and SFN SDRAM access within an approximately 4 KByte
17
for the implication of using PORT_ARB = 0. Refer to Errata
®
80314 I/O Processor Companion Chip Developer’s
®
SDRAM accesses.
Errata
25