EW80314GS Q 099 Intel, EW80314GS Q 099 Datasheet - Page 27

• Manufacturer Part Number: EW80314GS Q 099
• Manufacturer: Intel

Specifications of EW80314GS Q 099

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

45.
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Workaround:
Status:
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Problem:
Implication:
Workaround:
Status:
Intel
®
80314 I/O Processor Companion Chip Specification Update
External PCI/X DMA to SRAM sync packet
Sync packets from the PCI/X block to SRAM do not function correctly and can lead to data
corruption. During heavy fabric traffic, servicing of an external DMA interrupt can beat the actual
inbound data. The sync packet in this case is intended to ensure that inbound external DMA data
from the PCI/X block to the SRAM is flushed from the SFN fabric to SRAM before being accessed
by the Intel XScale
Section 4.2.6 of the Intel
Also see the white paper entitled Sync Packet Architectural Usage for the Intel
Processor Companion Chip (302325).
Since the PCI/X to SRAM sync packet does not work properly, external DMA must transfer data
only to/from SDRAM (PCI/X to SDRAM sync packets work).
External DMA data to SDRAM only. Updates by external DMA engines to descriptors located in
SRAM are allowable when access is coordinated by a semaphore type structure; in other words, a
CPU descriptor processing thread must not process a descriptor unless it sees that the external
DMA engine has set a “done” bit in the descriptor. Interrupt software, triggered by the external
DMA, must check for the descriptor “done” type bit to be set and issue a PCI/X to SDRAM sync
packet, before accessing the data in SDRAM.
No Fix
Possible lost interrupt due to read/write of aliased IACKx registers
Read or write access to offsets 0x304, 0x344, 0x384, and 0x3C4 in the PCI, CIU, GigE, and DMA
blocks are aliased to the MPIC IACKx registers 0x304, 0x344, 0x384, 0x3C4.
Unintended read or write access to the IACKx registers can cause an interrupt to be falsely
acknowledged and/or lost.
Only use DMA channel 3 for linked mode DMA/Memfill/XOR operation (direct mode not
allowed). Do not modify the following registers after initial setup.
In general, the conflicts with PCI, CIU, and GigE are benign, since it is expected that the
overlapping registers will not be modified after initial setup. The conflicting DMA registers are not
used if “chained” DMA mode is used. Be advised that even in “chained” DMA/Memfill/XOR
mode, a read or write of the ch3_src_addr_l, ch3_src1_addr_l, or ch3_src10_addr_l aliases to the
MPIC IACKx registers. DMA channels 0, 1, and 2 have no restrictions.
No Fix
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PCI LUT registers overlap:
CIU_SF_BAR1_LUTx registers overlap: 0x304, 0x344, 0x384, and 0x3C4
GigE RXQ 0 Buf Cfg overlaps:
DMA CH3_SRC_ADDR_L overlaps:
DMA CH3_SRC1_ADDR_L overlaps:
DMA CH3_SRC10_ADDR_L overlaps: 0x384
®
core. For more complete information on when sync packets are needed, see
®
80314 I/O Processor Companion Chip Developer’s Manual (273756).
0x304, 0x344, 0x384, and 0x3C4
0x384
0x304
0x344
®
80314 I/O
Errata
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