EW80314GS Q 099 Intel, EW80314GS Q 099 Datasheet - Page 22

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EW80314GS Q 099

Manufacturer Part Number
EW80314GS Q 099
Description
Manufacturer
Intel
Datasheet

Specifications of EW80314GS Q 099

Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
Errata
27.
Problem:
Implication:
Workaround:
Status:
28.
Problem:
Implication:
Workaround:
Status:
29.
Problem:
Implication:
Workaround:
Status:
30.
Problem:
Implication:
Workaround:
Status:
31.
Problem:
Implication:
Workaround:
Status:
22
Note: By design, 100 MHz PCI operation must always be driven by an external clock source, since in
Bus Number is not updated correctly in the PCI-X Status Register
The PCI-X Status Register at offset 0x0F4 bits[15:8] do not correctly update on a configuration
write.
The 80314 cannot respond to split transactions when configured from behind another bridge.
None
Fixed
PCIXCAP[1:0] = 01b is not a valid setting
A PCIXCAP[1:0] setting of 01b selects the incorrect internal clock phasing on the 80314.
PCI-X 50–66 MHz is not a valid mode using A0 silicon.
None
Fixed
Clock synchronization issues
A0 silicon does not always correctly handle clock-boundary transitions between the various
interfaces. Unpredictable behavior may result when data is transferred from one clock domain to
the next when the clocks are not synchronized.
All clocks must originate from a single clock source, and the CIU clock and SFN domains must run
at 100 MHz. For HBA designs, the SFN clock must be a multiple of the PCI input clock. For
embedded designs, the PCI clocks can be derived from either the same source as the SFN clock, or
from a clock output of the 80314.
100 MHz mode the PCI clock output of the 80314 is SFN clock/2.
None
Fixed
DMA channel hangs when it is stopped with STOP_REQ while CRC is
enabled
The DMA channel hangs and the ACT bit remains asserted. No data is transferred.
None
The channel can be reset and restarted without data impact, since the hang occurs only on the initial
read of the CRC (no data is transferred prior to the hang). Alternately, the situation can be avoided
by using the HALT_REQ bit instead of the STOP_REQ bit when utilizing the CRC functionality.
No Fix
5-volt tolerance
The 80314 is not 5-volt PCI tolerant.
Plugging the 80314 into a 33 MHz 5 V PCI bus draws excessive current, leading to damage and/or
device failure.
None. Do not design the 80314 into a 5 V bus/backplane. Also, do not connect 5-volt PCI devices
to either of the FL PCI interfaces.
No Fix
Intel
®
80314 I/O Processor Companion Chip Specification Update

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