EW80314GS Q 099 Intel, EW80314GS Q 099 Datasheet - Page 23

• Manufacturer Part Number: EW80314GS Q 099
• Manufacturer: Intel

Specifications of EW80314GS Q 099

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

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Intel
®
80314 I/O Processor Companion Chip Specification Update
Note: Refer to Errata
INT_PIN field PE_MISC2 00 for A0
The value of the PCI configuration register INT_PIN is 00 for the A-0 stepping and cannot be
changed.
The 80314 does not have the ability to instruct the PCI configuration software to assign an
interrupt.
Correct behavior would be as follows:
Where host enumeration source code is available, either modify the PCI configuration software to
recognize the 80314 and assign an interrupt without reading the INT_PIN register, or implement
polling in the host driver.
Fixed
Default SDRAM port arbitration setting can cause SFN starvation
The default setting 00b of the PORT_ARB field of the SD_CNTRL register can result in time-outs
on the SFN side when the CIU side is accessing the memory with repeated small requests (cache
off, coalescing disabled).
When the SFN side is starved of SDRAM access, the agent attempting accesses eventually times
out.
When using PORT_ARB = 00, ensure that the cache is on and coalescing on, or use one of the
alternative PORT_ARB settings.
No Fix
80/20 port arbitration is not functional
The 10b setting of the PORT_ARB field of the SD_CNTRL register [9:8] does not function
correctly. This setting provisions 80% memory bandwidth for CIU access and 20% for SFN access.
This setting is now reserved.
Under heavy system loads, use of the 80/20 PORT_ARB setting may cause data corruption, and the
system may hang.
Use only PORT_ARB 00*, 01* or 11 settings for B1 stepping. Use only 01 setting for A0/B0
steppings.
Clarification
No Fix
•
•
IRP_CFG_CTRL[LOC_INT_DEST] = 2'b01 INT_PIN = 8'h01
IRP_CFG_CTRL[LOC_INT_DEST] = 2'b00 INT_PIN = 8'h00
17
33
on the implication of using PORT_ARB = 01.
on the implication of using PORT_ARB = 00. Refer to Specification
Errata
23