EW80314GS Q 099 Intel, EW80314GS Q 099 Datasheet - Page 18

• Manufacturer Part Number: EW80314GS Q 099
• Manufacturer: Intel

Specifications of EW80314GS Q 099

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Errata
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18
Two Intel XScale
Only one interrupt output may be selected in the SEL_OUT field of the control registers for each
interrupt source.
When two Intel XScale
an interrupt.
When both cores require notification of an interrupt, one core must be specified as the target and
must use an application-specific mechanism to report the interrupt to the other core. Examples are
shared memory, use of the doorbell interrupt in the MPIC, and so on.
Fixed
DMA channel may require reset following SFN TEA errors
When a DMA receives a TEA from the SFN, a channel may get hung in the active state (DACT
asserted).
When a DMA channel is hung with DACT asserted, the DMA channel cannot be re-programmed
for another DMA transfer until it is soft-reset.
When firmware detects a TEA from the SFN, it must ensure that the DMA channel(s) affected are
soft-reset by means of the CHx_GCSR if they are hung with DACT asserted.
No Fix
Limitations on SFN outstanding transactions
When a read transaction is decomposed internally by the 80314 with one PCI-X bus master
controlling traffic to the other PCI-X block in embedded mode, all additional reads are held up
until there is only one remaining segment to be returned.
In a worst-case scenario, only one outstanding transaction that is 256 bytes (or misaligned
transaction > ~128 bytes) is serviced at one time.
None
Fixed
DMA and CRC32 or byte-swapping and CRC32 in a single operation may
corrupt data
Performing a DMA+CRC32 operation or ByteSwap+CRC32 with one of the PCI-X blocks as
source may corrupt the CRC because PCI-X read completions might complete out of order.
CRC32 cannot be calculated during a DMA operation with one of the PCI-X blocks as the source.
Byte swapping cannot be performed together with a CRC32.
The software workaround requires the data to be transferred from a PCI-X block to memory
(SDRAM or SRAM), and then have the CRC calculated in place as a separate operation. As long as
the data going into the DMA engine does not originate directly from a PCI-X block, the data can be
transferred to any location (including PCI-X) while calculating the CRC.
No Fix
®
Intel
®
cores cannot be the target of a single interrupt
cores are implemented in a single design, they cannot both be the target of
®
80314 I/O Processor Companion Chip Specification Update