EW80314GS Q 099 Intel, EW80314GS Q 099 Datasheet - Page 33

• Manufacturer Part Number: EW80314GS Q 099
• Manufacturer: Intel

Specifications of EW80314GS Q 099

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

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Affected Docs: Intel
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Affected Docs: Intel
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Affected Docs: Intel
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Affected Docs: Intel
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Affected Docs: Intel
Intel
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80314 I/O Processor Companion Chip Specification Update
Time-outs may result in data overwrites
17-bit timers are implemented to time-out SFN transactions that do not complete after a set period
of time. When a completion does come back after the time-out has occurred, data for one
transaction may overwrite another transaction. Transactions must not time-out beyond the range of
a 17-bit timer when the system is correctly configured. When these large time-outs occur, the
system-level issue must be addressed. When the timers cause problems, the PCI SFN timers can be
disabled.
The Intel
mechanism requires the use of SEEROM
There are two issues with the LOCKOUT bit functionality (bit 7 of the MISC_CSR register):
The implication of not retrying configuration cycles is that, when used on an HBA, a host may read
PCI resource requirements before the 80314 has programmed the P2S_PAGE_SIZES register. The
implication of the default value being set to 0 is that a host may attempt to configure the 80314
before firmware has changed this value to 1.
When the I
including configuration cycles are retried. Therefore, using the SEEPROM, it is possible to change
both the default value of the lockout bit as well as program the 80314 resource requirements
(P2S_PAGE_SIZES).
Intel
tested only to 3 GB
The 80314 is logically capable of supporting up to 12 GB memory but at this time has been
validated only up to 3 GB (3 × 1 GB DIMM).
Maximum I
The maximum supported size for data in EEPROM is 255 bytes (byte count field 0x00FE).
Proper handling of Gigabit Ethernet WAIT condition
Heavy Ethernet and SFN traffic resulting in slow interrupt response and/or insufficient data buffer
capacity may fail to free up Gigabit Ethernet RX buffers (receive queue) fast enough, triggering a
WAIT condition (data in FIFO but no buffers available). Use of the Abort function (ABT) from
within a WAIT service routine to flush the full or partial frame from the RX FIFO is not recom-
mended. Using this method to service a WAIT condition can corrupt the descriptor status and data
buffer contents. The recommended method to service a WAIT condition is for the WAIT service
routine to provide additional empty data buffers in the receive queue before re-enabling the queue,
thereby allowing the RX DMA to complete the transfer of the frame into memory.
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Setting the bit does not retry configuration cycles.
The default value is 0 instead of 1.
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80314 I/O Processor Companion Chip Developer’s Manual
80314 I/O Processor Companion Chip Developer’s Manual
80314 I/O Processor Companion Chip Developer’s Manual
80314 I/O Processor Companion Chip Developer’s Manual
80314 I/O Processor Companion Chip Developer’s Manual
80314 I/O Processor Companion Chip is capable of up to 12 GB but
2
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C/SEEPROM state machine is programming the 80314 register values, all cycles
80314 I/O Processor Companion Chip configuration retry
2
C memory
Specification Clarifications
33