EW80314GS Q 099 Intel, EW80314GS Q 099 Datasheet - Page 35

• Manufacturer Part Number: EW80314GS Q 099
• Manufacturer: Intel

Specifications of EW80314GS Q 099

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

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Issue:
Affected Docs: Intel
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Issue:
Affected Docs: Intel
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Issue:
Affected Docs: Intel
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Issue:
Affected Docs: Intel
Intel
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80314 I/O Processor Companion Chip Specification Update
Reset of Intel
host PCI/X reset
When configured for a host bus adaptor (HBA) application, resetting only the primary PCI/X
interface of the 80314 without resetting the entire host PCI/X bus can cause several issues,
including but not limited to high current draw and loss of proper PCI/X mode and frequency by
the 80314.
PCI/X cannot be the destination of a sync packet
Current documentation does not make it clear that the PCI/X block must not be the destination
(second specified port) of a sync packet; otherwise, the 80314 can behave incorrectly. Due to
PCI/X strict ordering rules, the sync packet is not required for the PCI/X block (write always
completes before a subsequent read).
SRAM enable/disable pin
The SRAM_SKU pin (AW33, previously listed as NC) is an input-only pin with an internal
pull-up. When this pin is tied low, the SDRAM inside the 80314 is inaccessible. When this pin is
left floating, the SRAM is accessible. “No SRAM” skew parts must tie this pin low. When this pin
is left floating, the device ID incorrectly indicates that SDRAM is usable.
Intel
Driver consideration for shared memory structures under PORT_ARB = 01
Due to the dual-ported memory controller of the Intel
must be taken to ensure sequence-dependent writes occur in order. For example, consider the case
where an Intel XScale
followed by an Intel XScale
tail of the descriptor chain. A system configured with the PORT_ARB = 01setting gives priority to
the fabric over the CPU. Due to this setting, under heavy fabric traffic, the CPU access to the
SDRAM can be held off in favor of fabric access to the SDRAM. The unintended result is that the
write to the NIC (over fabric) competes before the descriptor write to SDRAM. This signals the
NIC to start processing (read descriptor from SDRAM) before the descriptor setup write from the
CPU occurs.
The solution for PORT_ARB = 01 mode involves inserting a read between the SDRAM write and
the PCI/X agent writes. This works because ordering rules require posted writes to complete before
reads, and the Intel XScale
is delayed. Be careful that the read is to uncacheable/unbufferable SDRAM, so that the Intel
XScale
This is not an issue for the PORT_ARB = 00 setting because the Intel XScale
access to the SDRAM over the fabric, thus ensuring that the Intel XScale
completes before the PCI/X NIC write
This issue does not effect PORT_ARB = 11.
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80314 I/O Processor Companion Chip Developer’s Manual
80314 I/O Processor Companion Chip Developer’s Manual
80314 I/O Processor Companion Chip Developer’s Manual
80314 I/O Processor Companion Chip Datasheet
80314 I/O Processor Companion Chip Developer’s Manual
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port is forced to fetch data from SDRAM.
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80314 I/O Processor Companion Chip primary PCI/X without
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write to a PCI/X SDRAM NIC descriptor (descriptor command setup) is
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port stalls until the read returns from SDRAM, so the write to the NIC
write to the PCI/X NIC device to append the new descriptor to the
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80314 I/O Processor Companion Chip, care
Specification Clarifications
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write to SDRAM
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port has priority
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