EW80314GS Q 099 Intel, EW80314GS Q 099 Datasheet - Page 20

• Manufacturer Part Number: EW80314GS Q 099
• Manufacturer: Intel

Specifications of EW80314GS Q 099

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Errata
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20
Register swapping lock up
The following two combinations of BSWAP, WSWAP, and RGSWAP registers causes the 80314 to
lock up:
RGSWAP is not available without data swap.
None
Fixed
Enable Relaxed Ordering Bit attributes
The Enable Relaxed Order Bit (RO_EN) in the PCI-X Capability Register (PE_PCI/X_C) is
incorrectly reset to 0. This bit should be reset to 1.
None
Because the value is read/write, firmware may change the value to 0.
Fixed
Bus master enable bit not functional
Setting the Bus Master Enable bit to 0 in the PCI-X Command Register may not prohibit the 80314
from mastering transactions on the respective PCI-X segment.
Implications vary depending on usage/reliance of the BME bit.
None
Fixed
Remaining byte-count in split completion message may be incorrect
The 80314 may return the incorrect byte-count on a split completion message when both of the
following occur:
Some upstream bridges may use this byte count to optimize their own buffer usage.
None
No Fix
SDRAM bridging throughput performance limitations
There is an issue with the way the synchronization is done between the SFN and SDRAM clock
domains that may impact performance.
Performance through SDRAM (one PCI bus writing and one reading) is impacted by approxi-
mately 5%.
None
Fixed
1. A read is accepted that is greater than 1024 bytes, and
2. An error occurs in the first 256 bytes.
•
•
RGSWAP and WSWAP without BSWAP
RGSWAP and BSWAP without WSWAP
Intel
®
80314 I/O Processor Companion Chip Specification Update