WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 96

• Manufacturer Part Number: WG82577LM S LGWS
• Manufacturer: Intel

Specifications of WG82577LM S LGWS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 75.
Table 76.
Table 77.
Table 78.
Note:
89
IP Address Valid – IPAV
1. The IP address valid indicates whether the IP addresses in the IP address table are valid.
IPv4 Address Table – IP4AT
2*n (n=0, 1, 2)
1. The IPv4 address table is used to store the three IPv4 addresses for IPv4 request packets and directed IPv4
IPv6 Address Table – IP6AT PHY Address 01, Page 800, Registers 88-89 + 2*n
(n=0…3)
The IPv6 address table is used to store the IPv6 addresses for directed IPv6 packet
wake ups and manageability traffic filtering.
IP6AT can be used by the host.
Multicast Table Array – MTA[31:0] PHY Address 01, Page 800, Registers 128-
191
There is one register per 32 bits of the multicast address table for a total of 32 registers
(thus the MTA[31:0] designation). The size of the word array depends on the number
of bits implemented in the multicast address table. Software must mask to the desired
bit on reads and supply a 32-bit word on writes.
All accesses to this table must be 32-bit.
RO
RW
RW
RW
RO
RW
RW
RW
RW
Attribute
Attribute
Attribute
Attribute
packet wake ups. It is a 3-entry table with the following format:
31:0
0
31:0
1
2
3
4:14
15
Bit(s)
Bit(s)
Bit(s)
31:0
Bit(s)
0b
0b
0b
0b
0x00
0b
X
X
Initial Value
Initial Value
Initial
Value
X
Initial Value
Bit Vector.
Word-wide bit vector specifying 32 bits in the multicast address filter table.
1
PHY Address 01, Page 800, Register 64
Reserved
V41
IPv4 address 1 valid.
V42
IPv4 address 2 valid.
V43
IPv4 address 3 valid.
Reserved
V60
IPv6 address valid.
IPV6 Address
IPv6 address bytes n*4…n*4+3 (n=0, 1, 2, 3) while byte 0 is first on
the wire and byte 15 is last.
1
PHY Address 01, Page 800, Registers 82-83 +
IPADD
IP address n (n= 0, 1, 2).
82577 GbE PHY—Programmer’s Visible State
Description
Description
Description
Description