WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 38

• Manufacturer Part Number: WG82577LM S LGWS
• Manufacturer: Intel

Specifications of WG82577LM S LGWS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

6.4.2.3
31
Low Power Link Up (LPLU)
LPLU is a firmware/hardware-based feature that enables the designer to make the PHY
negotiate to the lowest connection speed first and then to the next higher speed and so
on. This power saving setting can be used when power is more important than
performance.
When speed negotiation starts, the PHY tries to negotiate for a 10 Mb/s link,
independent of speed advertisement. If link establishment fails, the PHY tries to
negotiate with different speeds. It enables all speeds up to the lowest speed supported
by the partner. For example, if the 82577 advertises 10 Mb/s only and the link partner
supports 1000/100 Mb/s only, a 100 Mb/s link is established.
LPLU is controlled through the LPLU bit in the PHY Power Management register. The
MAC sets and clears the bit according to hardware/software settings. The 82577 auto
negotiates with the updated LPLU setting on the following auto-negotiation operation.
The 82577 does not automatically auto-negotiate after a change in the LPLU value.
LPLU is not dependent on whether the system is in Vac or Vdc mode. In S0 state, link
speed battery saver overrides the LPLU functionality.
LPLU is enabled for non-D0a states by GbE NVM image word 0x17 (bit 10)
LPLU power consumption depends on what speed it negotiates at.
all of the power numbers for the 82577 in the various speeds.
• 0b = LPLU is disabled.
• 1b = LPLU is enabled in all non-D0a states.
82577 GbE PHY—Power Management and Delivery
Section 6.1
includes