WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 128

• Manufacturer Part Number: WG82577LM S LGWS
• Manufacturer: Intel

Specifications of WG82577LM S LGWS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

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121
Fields loaded from the NVM are set by the NVM only if the signature bits of the NVM's
Initialization Control Word match 01b.
This register, as well as the Extended Device Control register (CTRL_EXT), controls the
major operational modes for the MAC. While software writes to this register to control
MAC settings, several bits (such as FD and SPEED) might be overridden depending on
other bit settings and the resultant link configuration is determined by the 82577's
auto-negotiation resolution.
The FD (duplex) and SPEED configurations of the MAC are normally determined from
the link configuration process. Software might specifically override/set these MAC
settings via certain bits in a forced-link scenario; if so, the values used to configure the
MAC must be consistent with the 82577 settings.
Manual link configuration is controlled through the 82577's MII management interface.
Host Software Reset (bit 26), might be used to globally reset the entire host data path
and shared logic. This register is provided primarily as a last-ditch software mechanism
to recover from an indeterminate or suspected hung hardware state. Most registers
(receive, transmit, interrupt, statistics, etc.), and state machines are set to their
power-on reset values, approximating the state following a power-on or PCI reset. One
internal configuration register, the Packet Buffer Allocation (PBA) register, retains its
value through a software reset.
To ensure that the global device reset has fully completed and that the MAC responds
to subsequent accesses, programmers must wait approximately 1 ms after setting
before attempting to check to see if the bit has cleared or to access (read or write) any
other device register.
This register's address is also reflected at address 0x00004 for legacy reasons. Neither
the software driver nor firmware should use it since it might be unsupported in next
generations.
28
29
30
31
Bit
RW
RO
RW
RW/V
Type
82577 GbE PHY—Intel
0b
0b
0b
0b
Reset
Transmit Flow Control Enable (TFCE). Indicates that the MAC transmits
flow control packets (XON and XOFF frames) based on receiver fullness. If
auto-negotiation is enabled, this bit is set to the negotiated duplex value.
Reserved.
VLAN Mode Enable (VME). When set to 1b, all packets transmitted from
MAC that have VLE set is sent with an 802.1Q header added to the
packet. The contents of the header come from the transmit descriptor and
from the VLAN type register. On receive, VLAN information is stripped
from 802.1Q packets.
LAN Connected Device Reset (LCD_RST). Controls an inband message to
the 82577.
0b = Normal operation
1b = Reset to PHY is asserted.
The LCD_RST functionality is gated by the FWSM.RSPCIPHY bit. If the
FWSM.RSPCIPHY bit is not set to 1b, then setting the LCD_RST has no
impact. For proper operation, software or firmware must also set the
SWRST bit in the register at the same time. This bit is self-clearing.
®
5 Series Express Chipset MAC Programming Interface
Description