WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 150

• Manufacturer Part Number: WG82577LM S LGWS
• Manufacturer: Intel

Specifications of WG82577LM S LGWS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

10.2.1.3.3
Note:
143
Early Receive Threshold - ERT (0x02008; RW)
This register contains the Rx threshold value. This threshold determines how many
bytes of a given packet should be in the MAC's on-chip receive packet buffer before it
attempts to begin transmission of the frame on the host bus. This register enables
software to configure the early receive mode.
This field has a granularity of eight bytes. So, if this field is written to 0x20, which
corresponds to a threshold of 256 (decimal) bytes. If the size of a given packet is
smaller than the threshold value, or if this register is set to 0b, then the MAC starts the
PCI transfer only after the entire packet is contained in the MAC's receive packet buffer.
the MAC examines this register on a cycle-by-cycle basis to determine if there is
enough data to start a transfer for the given frame over the PCI bus.
Once the MAC acquires the bus, it attempts to DMA all of the data collected in the
internal receive packet buffer so far.
The only negative affect of setting this value too low is that it causes additional PCI
bursts for the packet. In other words, this register enables software to trade-off latency
versus bus utilization. Too high a value effectively eliminates the early receive benefits
(at least for short packets) and too low a value deteriorates PCI bus performance due
to a large number of small bursts for each packet. The RUTEC statistic counts certain
cases where the ERT has been set too low, and thus provides software a feedback
mechanism to better tune the value of the ERT.
It should also be noted that this register has an effect only when the receive packet
buffer is nearly empty (the only data in the packet buffer is from the packet that is
currently on the wire).
When early receive is used in parallel to the packet split feature, the minimum value of
the ERT register should be bigger than the header size to enable the actual packet split.
12:0
21:13
31:22
Bit
RW
RO
RO
Type
82577 GbE PHY—Intel
0x0
0x0
0x0
Reset
Receive Threshold Value (RxThreshold). This threshold is in units of eight
bytes.
Reserved.
Reserved. Reads as 0b. Should be written to 0b for future compatibility.
®
5 Series Express Chipset MAC Programming Interface
Description