WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 40

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WG82577LM S LGWS

Manufacturer Part Number
WG82577LM S LGWS
Description
Manufacturer
Intel
Datasheet

Specifications of WG82577LM S LGWS

Lead Free Status / RoHS Status
Supplier Unconfirmed
7.0
7.1
7.2
7.3
33
Device Functionality
Tx Flow
When packets are ready for transmission in the MAC it transfers them to the 82577
through the PCIe or the SMBus (depending on system state). The 82577 starts
transmitting the arrived packet over the wire after it gathers eight bytes of data if the
PCIe interface is active or after all packet data is received if it was transferred over the
SMBus; however, this behavior has no dependency on link speed. The 82577 design is
based on the assumption that the MAC has the full packet ready for transmission.
Rx Flow
The 82577 maintains a FIFO on the receive side in order not to lose packets when PCIe
is active. In this case, the 82577 initiates recovery of the PCIe when a reception has
started. If the link is at 1 Gb/s, the transmission of the packet over the PCIe bus starts
immediately after recovery. if the link speed is lower, the 82577 starts the transmission
after the entire packet is received.
Flow Control
Flow control as defined in 802.3x, as well as the specific operation of asymmetrical flow
control defined by 802.3z, is supported in the MAC. Some of the flow control
functionality has moved to the 82577. The following registers are duplicated to the
82577 for the implementation of flow control:
Flow control is implemented as a means of reducing the possibility of receive buffer
overflows, which result in the dropping of received packets, and allows for local
controlling of network congestion levels. This can be accomplished by sending an
indication to a transmitting station of a nearly full receive buffer condition at a receiving
station. The implementation of asymmetric flow control allows for one link partner to
send flow control packets while being allowed to ignore their reception. For example,
not required to respond to PAUSE frames.
• Flow Control Address is: 0x01, 0x80, 0xC2, 0x00, 0x00, 0x01; where 0x01 is the
• Flow Control Type (FCT): a 16-bit field to indicate the flow control type.
• Flow Control Transmit Timer Value (FCTTV): a 16-bit timer value to include in a
• Flow Control Refresh Threshold Value (FCRTV): a 16-bit PAUSE refresh threshold
first byte on the wire, 0x80 is the second, etc.
transmitted PAUSE frame.
value.
82577 GbE PHY—Device Functionality

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