WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 95

• Manufacturer Part Number: WG82577LM S LGWS
• Manufacturer: Intel

Specifications of WG82577LM S LGWS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Programmer’s Visible State—82577 GbE PHY
Table 72.
Table 73.
Table 74.
Shared Receive Address Low – SHRAL PHY Address 01, Page 800, Registers
44-45 + 4*n (n=0…3)
.
Shared Receive Address High – SHRAH PHY Address 01, Page 800, Registers
46-47 + 4*n (n=0…2)
Shared Receive Address High 3 – SHRAH[3] PHY Address 01, Page 800,
Registers 58-59
RW
RW
RO
RO
RW
RW
RO
RO
RW
RW
Attribute
Attribute
Attribute
31:0
15:0
17:16
30:18
31
15:0
17:16
29:18
30
31
Bit(s)
Bit(s)
Bit(s)
X
Initial
Value
X
0x00
0x00
0b
X
00b
0x00
0b
0b
Initial
Value
Initial
Value
Receive Address Low (RAL)
The lower 32 bits of the 48-bit Ethernet address n (n=0…3).
Receive Address High (RAH)
The upper 16 bits of the 48-bit Ethernet address n (n=0…3).
Address Select (ASEL)
Selects how the address is to be used. 00b means that it is used to decode the
destination MAC address.
Reserved, reads as 0b and is ignored on writes.
Address valid (AV)
When this bit is set, the relevant RAL and RAH are valid (compared against the
incoming packet).
Receive Address High (RAH)
The upper 16 bits of the 48-bit Ethernet address n (n=0…3).
Address Select (ASEL)
Selects how the address is to be used. 00b means that it is used to decode the
destination MAC address.
All Nodes Multicast Address valid (MAV)
The all nodes multicast address (33:33:00:00:00:01) is valid when this bit is
set. Note that 0x33 is the first byte on the wire.
Address valid (AV)
When this bit is set, the relevant address 3 is valid (compared against the
incoming packet).
Reserved, reads as 0x00 and is ignored on writes.
Description
Description
Description
88