WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 141

• Manufacturer Part Number: WG82577LM S LGWS
• Manufacturer: Intel

Specifications of WG82577LM S LGWS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Intel
10.2.1.1.19 Packet Buffer ECC Injection - PBECCINJ (0x01010; RW)
10.2.1.2
10.2.1.2.1
®
5 Series Express Chipset MAC Programming Interface—82577 GbE PHY
Interrupt Register Descriptions
Interrupt Cause Read Register - ICR (0x000C0; RC/WC)
This register is RC or WC. If enabled, read access also clears the ICR content after it is
posted to software. Otherwise, a write cycle is required to clear the relevant bit fields.
Write a 1b clears the written bit while writing 0b has no affect (with the exception of
the INT_ASSERTED bit.
11:0
23:12
24
31:25
0
1
2
3
4
5
6
7
8
9
11:10
12
13
14
15
Bit
Bit
RW
RW
RW
RO
RWC/CR/V
RWC/CR/V
RWC/CR/V
RO
RWC/CR/V
RWC/CR/V
RWC/CR/V
RWC/CR/V
RWC/CR/V
RWC/CR/V
RO
RWC/CR/V
RO
RWC/CR/V
RWC/CR/V
Type
Type
0b
0b
0b
0b
0b
0b
0b
0b
0b
00b
0b
0b
0x0
0x0
0b
0x0
0b
0b
0b
Reset
Reset
Transmit Descriptor Written Back (TXDW). Set when hardware processes a
descriptor with either RS set. If using delayed interrupts (IDE set), the
interrupt is delayed until after one of the delayed-timers (TIDV or TADV)
expires.
Transmit Queue Empty (TXQE). Set when, the last descriptor block for a
transmit queue has been used. When configured to use more than one
transmit queue this interrupt indication is issued if one of the queues is
empty and is not cleared until all the queues have valid descriptors.
Link Status Change (LSC). This bit is set each time the link status changes
(either from up to down, or from down to up). This bit is affected by the
LINK indication from the 82577.
Reserved.
Receive Descriptor Minimum Threshold hit (RXDMT0). Indicates that the
minimum number of receive descriptors RCTL.RDMTS are available and
software should load more receive descriptors.
Disable Software Write Access (DSW). The DSW bit indicates that firmware
changed the status of the DISSW or the DISSWLNK bits in the FWSM
register.
Receiver Overrun (RXO). Set on receive data FIFO overrun. Could be
caused either because there are no available buffers or because receive
bandwidth is inadequate.
Receiver Timer Interrupt (RXT0). Set when the timer expires.
LCAPD Exit Interrupt (LCAPD). Set when the Intel
Chipset takes the MAC out of LCAPD state.
MDIO Access Complete (MDAC). Set when the MDIO access completes.
Reserved.
PHY Interrupt (PHYINT). Set when the 82577 generates an interrupt.
Reserved.
Reserved.
Transmit Descriptor Low Threshold hit (TXD_LOW). Indicates that the
descriptor ring has reached the threshold specified in the Transmit
Descriptor Control register.
Address 0 Injection - Error injection first address in packet buffer.
Address 1 Injection - Error injection second address in packet buffer.
Enable ECC Injection to Address (ENACCADD). When set to 0b, the
addresses for ECC injection from this register are ignored.
Reserved.
Description
Description
®
5 Series Express
134