WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 145

• Manufacturer Part Number: WG82577LM S LGWS
• Manufacturer: Intel

Specifications of WG82577LM S LGWS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Intel
10.2.1.2.5
®
5 Series Express Chipset MAC Programming Interface—82577 GbE PHY
Interrupt Mask Clear Register - IMC (0x000D8; WO)
Software uses this register to disable an interrupt. Interrupts are presented to the bus
interface only when the mask bit is a 1b and the cause bit is a 1b. The status of the
mask bit is reflected in the Interrupt Mask Set/Read register, and the status of the
cause bit is reflected in the Interrupt Cause Read register (see
Software blocks interrupts by clearing the corresponding mask bit. This is accomplished
by writing a 1b to the corresponding bit in this register. Bits written with 0b are
unchanged (their mask status does not change).
In summary, the sole purpose of this register is to enable software a way to disable
certain, or all, interrupts. Software disables a given interrupt by writing a 1b to the
corresponding bit in this register.
0
1
2
3
4
5
6
7
8
9
11:10
12
13
14
15
16
17
18
19
20
21
22
31:23
Bit
WO
WO
WO
RO
WO
WO
WO
WO
WO
WO
RO
WO
RO
WO
WO
WO
WO
WO
WO
WO
RO
WO
RO
Type
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
00b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0x0
Reset
TXDW. Sets transmit descriptor written back.
TXQE. Sets transmit queue empty.
LSC. Sets link status change.
Reserved.
RXDMT0. Clears mask for receive descriptor minimum threshold hit.
DSW. Clears mask for block software Write accesses.
RXO. Clears mask for receiver overrun.
RXT0. Clears mask for receiver timer interrupt.
LCAPD. Clears mask for LCAPD interrupt.
MDAC. Clears mask for MDIO access complete interrupt.
Reserved. Reads as 0b.
PHYINT. Clears PHY interrupt.
Reserved.
Reserved.
TXD_LOW. Clears the mask for transmit descriptor low threshold hit.
SRPD. Clears mask for small receive packet detect interrupt.
ACK. Clears the mask for receive ACK frame detect interrupt.
MNG. Clears mask for the manageability event interrupt.
Reserved.
Reserved.
Reserved.
ECCER Clears the mask for uncorrectable EEC error.
Reserved. Should be written with 0b to ensure future compatibility.
Description
Section
10.2.1.3).
138