WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 70

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WG82577LM S LGWS

Manufacturer Part Number
WG82577LM S LGWS
Description
Manufacturer
Intel
Datasheet

Specifications of WG82577LM S LGWS

Lead Free Status / RoHS Status
Supplier Unconfirmed
Table 32.
63
Interrupt Mask Register - Address 24
1. MDINT_N is asserted (active low) if MII interrupt pending = 1b.
15:11
10
9
8
7
6
5
4
3
2
1
0
Bits
Reserved
TDR/IP Phone
MDIO Sync Lost
Auto-Negotiation
Status Change
CRC Errors
Next Page Received
Error Count Full
FIFO Overflow/
Underflow
Receive Status Change
Link Status Change
Automatic Speed
Downshift
MDINT_N Enable
Field
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Type
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
Default
82577 GbE PHY—Programmer’s Visible State
Reserved.
1b = Interrupt enabled.
0b = Interrupt disabled.
1b = Interrupt enabled.
0b = Interrupt disabled.
1b = Interrupt enabled.
0b = Interrupt disabled.
1b = Interrupt enabled.
0b = Interrupt disabled.
1b = Interrupt enabled.
0b = Interrupt disabled.
1b = Interrupt enabled.
0b = Interrupt disabled.
1b = Interrupt enabled.
0b = Interrupt disabled.
1b = Interrupt enabled.
0b = Interrupt disabled.
1b = Interrupt enabled.
0b = Interrupt disabled.
1b = Interrupt enabled.
0b = Interrupt disabled.
1b = MDINT_N enabled.
0b = MDINT_N disabled.
Description
1

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