WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 83

• Manufacturer Part Number: WG82577LM S LGWS
• Manufacturer: Intel

Specifications of WG82577LM S LGWS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Programmer’s Visible State—82577 GbE PHY
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
When 16 or more collisions have occurred on a packet, this register increments,
regardless of the value of collision threshold. If collision threshold is set below 16, this
counter won’t increment. This register only increments if transmits are enabled and the
82577 is in half-duplex mode.
Multiple Collision Count - MCC PHY Address 01, Page 778, Register 20 - 21
This register counts the number of times that a transmit encountered more than one
collision but less than 16. This register only increments if transmits are enabled and the
82577 is in half-duplex mode.
Late Collisions Count - LATECOL PHY Address 01, Page 778, Register 23 - 24
Late collisions are collisions that occur after one slot time. This register only increments
if transmits are enabled and the 82577 is in half-duplex mode.
Collision Count - COLC PHY Address 01, Page 778, Register 25 - 26
This register counts the total number of collisions seen by the transmitter. This register
only increments if transmits are enabled and the 82577 is in half-duplex mode. This
register applies to clear as well as secure traffic.
Defer Count - DC PHY Address 01, Page 778, Register 27 - 28
This register counts defer events. A defer event occurs when the transmitter cannot
immediately send a packet due to the medium busy either because another device is
transmitting, the IPG timer has not expired, half-duplex deferral events, reception of
XOFF frames, or the link is not up. This register only increment if transmits are
enabled. The behavior of this counter is slightly different in the 82577 relative to the
82542. For the 82577, this counter does not increment for streaming transmits that are
deferred due to TX IPG.
Transmit with No CRS - TNCRS PHY Address 01, Page 778, Register 29 - 30
This register counts the number of successful packet transmission in which the CRS
input from the 82577 was not asserted within one slot time of start of transmission
from the MAC. Start of transmission is defined as the assertion of TX_EN to the 82577.
31:0
31:0
31:0
31:0
31:0
Bit
Bit
Bit
Bit
Bit
RO/V
RO/V
RO/V
RO/V
RO/V
Type
Type
Type
Type
Type
0x00
0x00
0x00
0x00
0x00
Reset
Reset
Reset
Reset
Reset
MCC
Number of times a successful transmit encountered multiple collisions.
LCC
Number of packets with late collisions.
COLC
Total number of collisions experienced by the transmitter.
CDC
Number of defer events.
TNCRS
Number of transmissions without a CRS assertion from the 82577.
Description
Description
Description
Description
Description
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