WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 165

• Manufacturer Part Number: WG82577LM S LGWS
• Manufacturer: Intel

Specifications of WG82577LM S LGWS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Intel
10.2.1.4.3
Note:
10.2.1.4.4
10.2.1.4.5
®
5 Series Express Chipset MAC Programming Interface—82577 GbE PHY
Adaptive IFS Throttle - AIT (0x00458; RW)
Adaptive IFS throttles back-to-back transmissions in the transmit packet buffer and
delays their transfer to the CSMA/CD transmit function, and thus can be used to delay
the transmission of back-to-back packets on the wire. Normally, this register should be
set to zero. However, if additional delay is desired between back-to-back transmits,
then this register might be set with a value greater than zero.
The Adaptive IFS field provides a similar function to the IPGT field in the TIPG register
(see
transmission timing.
If the value of the AdaptiveIFS field is less than the IPGTransmitTime field in the
Transmit IPG registers then it has no effect, as the chip selects the maximum of the two
values.
Transmit Descriptor Base Address Low - TDBAL (0x03800 + n*0x100[n=0..1];
RW)
This register contains the lower bits of the 64-bit descriptor base address. The lower
four bits are ignored. The transmit descriptor base address must point to a 16-byte
aligned block of data.
Transmit Descriptor Base Address High - TDBAH (0x03804 +
n*0x100[n=0..1]; RW)
This register contains the upper 32 bits of the 64-bit descriptor base address.
15:0
31:16
3:0
31:4
31:0
Bits
Bits
Bits
Section
RW
RO
RO
RW
RW
Type
Type
Type
10.2.1.5.2). However, it only affects the initial transmission timing, not re-
0x0000
0x0000
0x0
X
X
Reset
Reset
Reset
Adaptive IFS value (AIFS). This value is in units of 8 ns.
Reserved. This field should be written with 0b.
Reserved. Ignored on writes. Returns 0b on reads
Transmit Descriptor Base Address Low (TDBAL)
Transmit Descriptor Base Address [63:32] (TDBAH).
Description
Description
Description
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