WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 81

• Manufacturer Part Number: WG82577LM S LGWS
• Manufacturer: Intel

Specifications of WG82577LM S LGWS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Programmer’s Visible State—82577 GbE PHY
8.6
Table 41.
Table 42.
Table 43.
Port Control Registers (Page 769)
Custom Mode Control PHY Address 01, Page 769, Register 16
Port General Configuration PHY Address 01, Page 769, Register 17
Power Management Control Register PHY Address 01, Page 769, Register 21
Reserved
MDIO Frequency Access
Reserved
Tx Gate Wait IFS
BP extension Wait
Reserved
Active_PD_enable
Reserved
Host_WU_Active
Wakeup clocks stop
MACPD_enable
Reserved
Reserved
Collision threshold
Retry late collision
Name
Name
Name
0x04
0b
0x180
01110b
100b
0b
0b
1b
0b
1b
1b
00b
0x00
0x0F
0b
Default
Default
Default
15:11
10:8
7
6
5
4
3
2
1:0
15:9
8:1
0
15:11
10
9:0
Bits
Bits
Bits
Reserved
0b = Normal MDIO frequency access.
1b = Reduced MDIO frequency access.
Note: Required for read during cable
disconnect.
Reserved
Determines the size (in nibbles) of non-
deferring window from CRS de-assertion.
Additional waiting byte times after TX Gate
Wait IPG expires until the Back Pressure In-
band bit is cleared.
Reserved
Active Power Down Enable (sD3 Enable)
When set to 1b, the Intel® 5 Series Express
Chipsetneeds to enter MAC power down
mode.
Reserved. This bit is reset by power on reset
only.
Enables host wake up from the 82577. This
bit is reset by power on reset only.
Wake-up clocks are stopped while wake up is
disabled.
Written as 1b when the Intel
Express Chipset needs to globally enable the
MAC power down feature while the 82577
supports WoL. When set to 1b, pages 800
and 801 are enabled for configuration and
Host_WU_Active , ME_WU_Active are not
blocked for writes.
Reserved
Reserved, write to 0x00
Number of retries for a collided packet.
Retry late collision.
Description
Description
Description
®
5 Series
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
R/W
R/W
R/W
R/W
R/W
Type
Type
Type
74